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In the double pulse test I'm carrying out in simulation, there is a huge current spike in the current when the N-MOSFET turns on. What could be the reason?

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    \$\begingroup\$ This is the main idea behind double-pulse test: bring the inductor in continuous conduction mode after a first energizing pulse and while the upper-side body diode (or a simple diode) free-wheels, you brutally turn it off by actuating the low-side transistor. The current spike you see is the current inherent to the blocking mechanism of the diode which becomes a short circuit before recovering its blocking capability. The test is used to either characterize the diode or check losses on the low-side transistor. Slowing down the low-side transistor will affect the spike amplitude. \$\endgroup\$ Oct 18, 2023 at 8:31
  • \$\begingroup\$ Hi! @VerbalKint, will this high amount of current (300A-400A) affect the pcb (components in pcb)/test setup? (within nanoseconds) \$\endgroup\$
    – Andr7
    Oct 18, 2023 at 8:33
  • \$\begingroup\$ You will find this EE question interesting: electronics.stackexchange.com/questions/649763/… \$\endgroup\$
    – MiNiMe
    Oct 18, 2023 at 10:23
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    \$\begingroup\$ @Anshhh7 That high amount of current won't actually exist on a real PCB, due to parasitic inductances that aren't modelled. Look at the slew rates involved, a handful of nanohenries would tame that spike. There'd still be high current, just not quite that hight. \$\endgroup\$
    – Hearth
    Oct 18, 2023 at 12:45
  • \$\begingroup\$ Thanks @Hearth! How can I actually model the parasitics? \$\endgroup\$
    – Andr7
    Oct 19, 2023 at 5:13

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It's called reverse recovery, a property of the body diode of the high-side MOSFET, when hard switching occurs (current suddenly reversing by opposing switch turn-on).

Note that SPICE is notoriously poor at simulating reverse recovery; a charge-dependent hack is used, which gives acceptable results for modest dI/dt rates, but gives significant error for typical parts switching near their rated switching times (so, 10s to 100s ns). Forward recovery is not modeled either, though in my experience, body diodes exhibit little so this isn't much of a problem.

Of note, the loop inductance probably isn't well modeled here, which likely limits turn-on dI/dt and peak current much more than shown here, even with extremely powerful gate drive.

Loop inductance likewise causes voltage overshoot after diode recovery finishes, so must be managed by appropriate component choice, drive strength, and PCB layout.

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