I adjusted the clearance values, and that did not fill in the gap.
As other comments have said, this is not a clearance issue but rather a function of the thermal reliefs that EAGLE applies to polygon pours. Using the info tool, click on the polygon outline, and uncheck the box that says Thermals in the Polygon Section. Make sure you understand the pros and cons of using thermal reliefs though, there are times when they are not needed and times when they can save you a lot of hassle.
The other answers correctly identify this as being to do with thermal relief settings. You can either disable
Thermals setting in the properties for that small polygon.
Alternatively you can modify the
Thermal isolation setting in the DRC to reduce the gaps, though this may not be possible depending on you fabs capabilities, and affects the whole board.
On a related note, there is another issue with that polygon. Note the clearance errors around the bottom of the polygon:
This is because both the small polygon and the one below it have the same
The rank of the polygon specifies the order in which the polygons are filled. Those with a higher rank number are filled later and will therefore pull back from polygons with a lower number.
When two polygons with equal rank number overlap each other, they will not correctly respect the minimum clearances and hence you get the DRC error. To fix this, you should change them to have different
rank numbers in the polygon properties (you could also manually adjust the edges of the polygon for more clearance, but rank is sufficient).
This gap is part of the thermal reliefs you've applied to the pad or the zone. I don't use Eagle, so I can't tell you how to change it, but it's likely a setting either in the pad, the zone, or the footprint settings--just turn off the thermal reliefs for that pad if you need a solid connection.