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I'm working on EMC testing a product. We have an internal 30 cm ribbon between 2 boards. One has a MCU and LCD, and the other MOSFETs and a 3 A switching regulator.

We determined that a lot of RF is radiating from the cable, likely originating in the MCU board. The emissions are mostly broadband 30-100 MHz.

We were able to drastically reduce this by adding a clip-on ferrite with 2 turns of the ribbon cable.

If I wanted to replicated this effect using SMD components, what would be the best practice?

The signals in the ribbon cable are very low-frequency and low-current. The highest is 16 kHz, digital. The rest are below 500 Hz PWM. There 2 GND wires and 2 5V wires carrying about 1A in total.

An example solution: use an SMD common-mode choke on the power, and use series resistors on the other lines.

I only had time to take one crack at it. I put ferrite beads on all signals (including ground). This helped, but not a ton. What should I have done?

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    \$\begingroup\$ The symptom sounds like either there are other connections (not just the ribbon) to the board(s), the signals are completely unfiltered, or the grounding within one or both boards is very poor. It is impossible to tell without schematics and layout: could you provide these? \$\endgroup\$ Oct 21, 2023 at 3:16
  • \$\begingroup\$ There's more to it than just the ribbon. But I'm basically asking: How would I can get a similar effect to the clip on ferrite on the pcb. \$\endgroup\$
    – Drew
    Oct 21, 2023 at 3:37
  • \$\begingroup\$ I'm certain the ferrite on the ribbon is effective, because we tested with and without it in an an anechoic chamber. \$\endgroup\$
    – Drew
    Oct 21, 2023 at 3:42
  • \$\begingroup\$ Well, the easiest is to put everything on a multiwinding transformer and parallel that with a ferrite bead to set the impedance. But we can't know if that's a feasible solution. You also ask "best practice", but best is not to make a substitution, it's avoiding the problem in the first place. \$\endgroup\$ Oct 21, 2023 at 12:14
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    \$\begingroup\$ I think TimWilliams is right. If you are going to modify the PCB anyway, it will likely be cheaper to modify it so that it does not require separate filtering so you don't need to add expensive filtering components. But if you only tried a clamp on ferrite and it made the device pass, then that's the fastest way to pass testing and sell the product. Update to new version later with a better and cheaper design. \$\endgroup\$
    – Justme
    Oct 22, 2023 at 14:08

1 Answer 1

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A cable bead provides common-mode impedance.

That is, it's a multiwinding transformer, with a fairly large \$k\$ between windings, and an impedance in parallel with them, which we can consider as magnetizing inductance and core loss. There's also a capacitance term, whether through the core itself (dielectric constant of ferrite is fairly middling actually, and being moderately conductive, the constant is effectively complex-valued, but also not constant but frequency-dependent, but I digress), or due to overlap between windings (particularly for the multi-turn case).

Individual ferrite beads are a poor substitute, because, depending on what the signals are, they may act in parallel, or not at all: supply and ground pins are wired in parallel (directly or by bypass caps at either end), while high-impedance signals carry no current and therefore little voltage drop across its bead. (Signal impedance is limited by cable impedance, depending on electrical length, so this is most true for short cables and low frequencies.) And of the beads that do act in parallel, well, they act in parallel: the impedance goes as 1/N for N in parallel. So even if you use large value say 1-2kΩ beads, ten in parallel is only just as much as a thick cable bead, let alone two turns (approx. 4x impedance, but peak impedance a bit lower than that, and at lower frequency, due to capacitance as mentioned) or more.

The direct substitute, then, is to use transformers on board.

And... yes, it can be done, but do you really want to do it this way? As if to give proof by contradiction... let's give it a try, eh?

I actually built this once, on a design that was going straight to the customer; I wasn't going to be involved with EMC, so I wanted to give them enough options to play with, and a good chance of passing on the first try. (Which was probably wasted effort in the end; no one asked me what the components were for, or what values to suggest for changing them, or when.)

enter image description here

The ISO- signals, and supplies (logic supply, a higher voltage, and two GNDs), arrived on board via 2x5 pin header and ribbon cable. As you can tell from the net names, this was an SPI interface, so, one end driven, other ~open circuit. Because of the modest bandwidth (some Mbps), significant filtering was not an option (recall, conducted EMI is tested down to 150kHz), so I opted for a CMC approach instead, at least as the preferred option (this was the build as-tested).

The top components are for other options: C11-R47, an RC between grounds to dampen voltage across the isolation barrier (there was also a fully isolated option); R41, R45 and R46 (and others in the power supply section, not shown), jumpers to join the ground planes; and R24-R28 and R30, termination / filtering resistors spanning the gap. There are also non-populated test points for automated and manual/prototype electrical testing.

Only the lower half, with CMCs and RCs, was installed in the board as-ordered.

The PCB layout was:

enter image description here

The 2x5 header was placed off to the bottom-right corner; a strip of ground plane follows traces off to the connector. The bulk of the board proper extends left, up and right, wrapping around this interconnect area.

Again, probably overkill -- but one must be careful when making slots in ground planes. Which includes isolation especially, which was a potential option here, so you get to see an over-the-top belt-and-suspenders approach.

Key insights:

  • Signals flow over a ground/reference plane.
  • Signals flow with some impedance to ground, inducing an image current in the plane. A signal flowing over a gap between planes, has to have that image current return through a circuitous route around the gap, or induces a voltage drop between planes. Most generally, it's a coupling from signal trace to the between-planes environment, and current and voltage manifest between planes depending on the impedance joining them.
  • Different planes have different voltages between them, due to the common-mode between connected cables, induction through isolation components, from nearby fields, etc.

There is very good justification to treat local ground planes as wholly isolated environments, with the adjustment that galvanic connections between planes may be acceptable -- more specifically, that whatever happens at galvanic frequencies (DC/mains), is irrelevant to, and separable from, what happens at signal frequencies (MHz+).

Notice these principles extend onto cables themselves, so it is preferable for example to use shielded cable (with the shield tied to PCB ground plane as intimately as possible*) than bare ribbon/twist/multiconductor, when signals will be susceptible to common mode interference.

An effective shield shall be a topological extension of the PCB ground plane.

*Again, at RF; galvanic frequencies are irrelevant. If you need some voltage offset at LF (say to avoid ground loop), coupling/bypass capacitors can be used to join the grounds at AC. Whether this causes further problems (there is some leakage due to capacitor ESL; maybe capacitance isn't tolerable at LF) is another matter, but this is just what is important at AC.

Anyway, lacking shielding, we consider the common mode choke approach.

Given that there will be some (AC) voltage between planes, we can maintain signal quality by inducing an equal voltage in series with each signal line, and only then, crossing the gap between planes.

The signals, and image currents, are carried upon CMCs, so that we aren't inducing signal currents between the planes.

The only major challenge is getting all those signals together. Two-line data chokes are cheap and plentiful; more lines are suddenly expensive, or come with nasty limitations (like, parts sold as CMCs, but they're really just independent or at least weakly coupled ferrite beads; multi-aperture cores and ferrite chip arrays come to mind).

So, two-line data chokes it is. These have high \$k\$, so we can induce that ground-loop voltage quite effectively, while also communicating the signal/image current effectively, so that's covered nicely. But what about coupling all of them together?

We need N transformers for N signals, plus separate coupling for power and ground.

Since we don't have a common transformer core, we use N independent cores, with one winding tied in common between all of them: this is the ISOGND to ISOGND2 connection.

We DO NOT connect power through data chokes: they will saturate. These parts (Pulse PE-1812ACC510STS) saturate at around 50mA, so any imbalanced DC is a huge problem. At the very least, we cannot use the same connection (one winding for signal/power, one to induce the CM voltage). As a result, C31, C26 and R38 provide AC bypass only, and some damping. (Notice also, they are placed roughly 1/3 and 2/3 along the ISOGND2 trace, which wraps around the inside edge of the isolation slot. This keeps stray inductance low, from any particular transformer to either bypass.)

Instead, power and ground are joined elsewhere, in the power supply section. A power/data type CMC was used (Bourns SRF0905 series). Signal currents are nil (DC), and power supply dominates (couple amperes), making this an effective solution.

Ground does not need to be joined locally, around where the signals connect, specifically because the CMCs handle that. Ground must be connected somewhere, and do not misunderstand the above schematic as if grounds aren't connected at all (which they're not, on that sheet, but this connection is shown on another sheet); or as if they were connected locally (which they're not, those components are DNP as mentioned above).

Like, even just the matter of communicating these tricks, whether on the schematic level (keeping track of exactly which connections are made where), or documentation level (as in, right here), is good reason to consider a simpler solution. Not to mention the area taken up (the layout area in question is about 22 x 37mm across), or the parts cost (there's a good $3 or so of parts taken up in this section alone).


What's the preferred way, then?

From the question,

The signals in the ribbon cable are very low-frequency and low-current. The highest is 16 kHz, digital. The rest are below 500 Hz PWM. There are two GND wires and two 5 V wires carrying about 1 A.

it sounds like signals could simply be filtered and that's it.

At a guess, I suppose you've got signals driven directly by a logic IC or MCU, and they're spraying RF all over the place, because the "highest frequency" is not the repeat rate, it is the edge rate. Which for such devices is well under 10ns, with 1-3ns being typical of medium-capability MCUs. Thus your bandwidth limit is actually more like 200MHz, and it's no accident you failed emissions, you practically intended it by hanging an antenna off these pins!

Key insight: Only use what bandwidth you need.

If you don't need the full drive strength of a GPIO, set it to lower, or minimum. Add an RC, or LC (typically with ferrite bead) filter. Add ESD protection too (clamp diodes, TVS array, etc.) while you're at it.

A ribbon cable is nothing but bare naked wires spanning across space; there is modest coupling between adjacent wires, but even if it were 99% coupling, that's still 1% of a 15kV ESD surge coming straight into your ICs. Granted they can withstand, whatever, maybe 2kV or so (HBM, though the impedance is different in the cable too), though that's also in an unpowered state, and may exhibit a class C failure mode (requires power cycle to recover). But a real cable is more like 80 or 90% coupling. And a TVS diode will take that down to a few dozen volts, instead of thousands. And then the RC filter knocks that down to ~mA at the chip, no damage, no latchup.

The same argument applies to radiated and conducted susceptibility, of course. Particularly if you want to maintain low-error communication, then either adequate filtering must be applied, or shielding, or anything equivalent to that (differential pairs and a good signaling standard, like RS-422, do about as well as a poorly shielded cable).

Since you imply the signals are (supposed to be) very slow, simply RC filtering them with appropriate values -- some kohms and nF perhaps -- likely will do everything that is needed. There might still be problems with poor grounding, ground loop, other cable connections, etc., I have no idea.

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  • \$\begingroup\$ Thank you for the very thorough response! \$\endgroup\$
    – Drew
    Oct 23, 2023 at 17:51

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