Let us consider this worst-case loop for example:
When Q2 turns off, the current flowing in this loop suddenly changes direction, and thus a large EMF develops around the enclosed area (and nearby). The figure appears to be around 180 DPI so we can measure the wider loop as about 2.1 x 2.2", the smaller loop as 0.9 x 1.5", and W1 appears to rise quite far above the board so add some extra for that as well. Round loops of about these dimensions give inductance on the order of 75 and 40nH respectively, and, let's say 30nH for W1, for a total of 145, round it to 150nH then. (There's also a good 10nH or so for each TO-220, but whatever.)
If for example, we have 4A switching in 50ns, 80A/us through 150nH is 12V dropped. Not very threatening to Vds ratings fortunately, but the Coss of the IPP60R360P7 and CJ of the diode -- which, uh, did you mean to put in 200V parts, BYV79E-200?? -- form a resonant circuit in this loop which will resonate at quite high frequency, in response to step changes. (Note that, due to the snappy effect of the transistors' Coss, the VDS rise/fall edge can be many times faster than for current.) This is true at turn-on as well, give or take if load current appears immediately, or delayed by significant leakage in T1, and how that current distributes through the loop.
And note that a portion of this loop is common between any likely oscilloscope probe targets, and the mains input (which has no filtering whatsoever), so we can reasonably expect a huge amount of common-mode noise as well. Maybe not huge in comparison to the output switching waveform, but a significant part of the gate signal perhaps. In other words: what you measure, might not be the actual gate waveform at that point in the circuit, but worse still, the act of connecting the probe to measure it, actively worsens signal quality (that is, because of CM current through the ground clip).
Put another way: presumably you have an isolation transformer in front of this thing, and yes it's galvanically isolated (i.e. at DC/mains freq.), but when is isolation not isolation? When the impedance across the barrier is significant. There is capacitance, and also the wiring, the board itself, or the scope and probes (if they are isolated instead / as well), have capacitance, and so the whole matter of isolation goes somewhat out the window as frequency goes up.
Common mode is easy enough to recognize by probing: simply probe the ground clip. One assumes a short-circuited probe reads nothing, but in fact the ground clip itself has inductance (and the cable is also "leaky" to some extent) and thus you're reading the voltage drop along that wire, as a consequence of high-frequency currents flowing in the loop between oscilloscope and EUT input, output or other connections.
You can also read loop voltage by shorting out the probe in this way, and hovering the resulting one-turn loop antenna over the circuit. You will measure significant transients around the highlighted area.
As for what to do with it?
Frankly, I never would've built the PCB as shown; it should've gone through a design review, back and forth until an acceptable layout is had. This is, of course, not a luxury students typically have, and you can -- and should indeed -- consider this part of the learning experience. (So, citing these answers in your report/thesis would be prudent, as well. :) )
A single-layer build is still not unreasonable at this power level, but two or more is much easier to lay out and debug, and is essentially no extra cost (1 vs. 2 layers that is; 4 vs. 2 is about double cost, kinda for obvious reasons). Assuming of course you have proto services available (are Chinese vendors really not available down there?). But even a hand-made board (as this appears to be!) is reasonable to make in 2 layers, given some extra considerations about thru holes (since edge plating is several extra steps, requiring some special materials); you'd probably use riveted vias, or solder wires in as vias before placing THT components, so you don't have to have their leads soldered on both sides.
The build might not be scrap outright, but it will definitely not work at best possible performance; expect compromises in efficiency and power density.
The most likely steps are to drastically shrink the loops in question:
Add the CBs in the locations shown. 0.1µF PE or PP film will be sufficient. They might also need some ESR to dampen against the larger inductive loop; in that case, around an ohm would be appropriate, particularly on the bottom one.
RCs can be used to further dampen the loops around each component, relevant during respective turn-on / turn-off events. Typical starting values would be 100pF and 33Ω, and adjust values until the transients are acceptable. Note that lead lengths must be kept short, for the same reason as before: you want minimum inductance in these components. Use C0G ceramic or PP film, and, probably a 1/2 to 1W metal-oxide resistor.
You can further constrain dV/dt by adding an R+C between drain and gate; the effect of this depends on gate drive resistance, with typical starting points of, let's say, 100 ohms RG, and 10pF and 1k D-G.
A ferrite bead looped over the source pin can also be used to slow dI/dt, or over the drain pin, or either diode pin, to dampen their respective loops (high frequency ringing).
Aside: are you sure about output current sensor placement? If it were in series with L1, you could do average current mode control, greatly improving loop dynamics and transient/startup/fault robustness.