# Output level of common-source amplifier with PMOS load

Let's consider the common-source amplifier circuit above (left). This circuit does not have a well-defined output level. This part is easy to understand. In the book by Razavi, he says this "stage is reliably biased only if a feedback loop forces $$\V_{\text{out}}\$$ to a known value".

The circuit on the right shows the CS stage with feedback. I understand that feedback across M1 causes M1 to adjust its gate-source voltage so that the current produced by M1 matches the current produced by M2. What I don't understand is how "the feedback loop forces $$\V_{\text{out}}\$$ to a known value". How does the feedback loop force $$\V_{\text{out}}\$$ to a known value? The only way I can think this would work is by choosing $$\R_1\$$ and $$\R_F\$$ to be very small values. In that case, it is as if $$\V_{\text{in}}\$$ is connected directly to $$\V_{\text{out}}\$$. But this causes a big problem: the circuit has no more gain. On the other hand, if we make $$\R_1\$$ a large value and $$\R_{\text{out}} = \alpha \cdot R_1\$$, where $$\\alpha > 1\$$, we have some gain, but then how do we force the output level "to a known value"?

When the input Vin is increased, it causes Vout to decrease. Now, the gate of M1 is a remarkably high gain point with little range. By increasing Vin, Vout decreases, and through Rf compensates by reducing the voltage at the gate of M1.

If the gain at the gate is extremely high, Rf/R1 will be the resulting gain of the circuit, as each perterbation of the input will change the output until the preferred voltage at M1's gate is restored.

Of course gain is never infinite, but for a first approximation this is a reasonably safe assumption as long as the open loop (without Rf) gain is much higher than the closed loop (with Rf) gain.

• Thanks for responding, but your reply did not address the question I asked. I already mentioned that I understand how feedback works in this circuit. My question was specifically on how the "feedback loop forces $V_{\text{out}}$ to a known value". Commented Oct 23, 2023 at 20:49
• It doesn't "force it to a known (constant) value," but to a value determined largely by the value of the input. The quote about forcing the output is poorly phrased, but what they're trying to say is that it makes the output more predictable. Without the feedback, the output depends much more strongly on the less predictable exact values of the gate threshold voltage and transconductance, which can vary significantly not only from one part to another, but within the same individual device over the specified range of environmental conditions. Commented Oct 24, 2023 at 14:00

The simplest example I can think of to illustrate this is as follows:

You fix a $$\V_{gs}\$$ voltage at the left $$\M_1\$$. You get a current $$\M_1\$$ flowing, but you have no idea what is it: process variation, temperatures, etc will determine what's the actual current flowing through it. At the top, you have a current source. This source, by definition, must keep sourcing the same current no matter what the voltages at its terminals are, i.e. it doesn't define any node voltage.

On the other hand, with the feedback loop, you have a clear mapping between $$\V_{gs}\$$ and $$\I_{ds}\$$. Remember that feedback loops need a sense and a control mechanism to function properly.

If $$\I_{ds}\$$ increases and causes a change in $$\V_{ds}\$$, this will be sensed by the gate with a swing of the opposite sign. Assuming a very crude low frequency NMOS small-signal model (just a $$\g_m\$$ and a $$\r_o\$$), a change in $$\V_{gs}\$$ (say, due to a change in the gate voltage; the source is fixed to ground), $$\\Delta V_{gs}\$$, will cause a change, at the same node, given by:

$$-\Delta V_{gs}\frac{g_mr_oR_1}{R_1+R_f+r_o}$$

This simply means the output is acting up to suppress the swing at $$\M_1\$$'s gate. When the opposing signal is at the gate, then it is kept at its nominal $$\V_{gs}\$$ voltage and thus, the output current is also kept constant after the feedback has acted up.

Now, how does the $$\M_1\$$'s drain know where to settle? Well, at startup, all we know is that there will be a current flowing through the circuit due to the current source $$\M_2\$$. This current will begin flowing through the $$\R_F-R_1\$$ branch first and $$\M_1\$$ later. $$\M_1\$$'s gate voltage will increase and this will allow more current to flow through it. There will be a point where the most of the current from the current source will flow through $$\M_1\$$'s drain, and what's left through the $$\R_F\$$-$$\R_1\$$ to keep it biased at fixed voltage.

Whatever the drain voltage is, the gate voltage will be determined by simple voltage division $$\V_{ds}\frac{R_1}{R_1 + R_F}\$$ (assuming negligible current through the gate).

As a bonus, you'll probably notice that this circuit is the MOS equivalent of the so-called $$\V_{be}\$$ multiplier. Just take a look at them, they are exactly the same, except for the transistor type.

In short, feedback allows nodes to have very little swing as the loop only function is to suppress them, this is what keeps all transistors properly biased. Obviously, the last stage of any multi-stage amplifier is the one with the largest swings, as it probably has to output a large voltage. That's why they usually dominate distortion and small-signal analysis is not that accurate in such stages.

The voltage, Vout, will settle such that the voltage at the gate of M1 causes the M1 current to match that of M2 (ignoring the current through RF).

This voltage will be a function of Vin, M1 threshold voltage, M1 gm and the ratio of Rf and R1.