I'm trying to design a board that will accept UART/8N1 input from another board at 3.3V. While the two boards share a common GND (obviously), they otherwise have totally independent power supplies: one is powered by USB VBUS which is regulated down to 3.3V, and the other by an AC adapter that is independently regulated down to 3.3V.
My question is this: obviously the two different 3.3V rails are not going to be at exactly equal potentials. Both have some amount of ripple, both will be experiencing load transient spikes at various times, no regulator is perfectly accurate, there are thermal de-rating effects, etc. Therefore, when connecting the GPIO output pin from the other board to the GPIO input pin on my board, do I need a current-limiting resistor in series with the signal? Do I need a low Vf diode to prevent current back flow out of my board through the GPIO?
Here is a diagram that I hope makes the situation clearer:
Both the output GPIO (on "Other Board") and the input GPIO (on "My Board") are based on similar Lattice ECP5 FPGAs, and the datasheet for this FPGA family says that IO pins can handle voltages above or below 3.3V by an absolute maximum of about 300mV or preferably no more than 165 mV under recommended operating conditions. Since the voltage regulators used on the two boards both respond to load step transients with a max of about +/-50mV and have ripple deviations of less than that, I'm not concerned that the two voltage rails will deviate substantially -- except in the case where one board is powered off completely and the other is up and running.
What I am mainly trying to understand is whether there can be current flow between an input GPIO pin and an output GPIO pin given that one board's 3.3V rail may actually be 3.25V while the other board's 3.3V rail may actually be 3.35V. It would seem to me that in this case, which is going to be happening all the time, current flow would flow from the slightly higher 3.35V voltage rail to the slightly lower 3.25V rail through the GPIO line? (I can't find anything in the datasheet that says that single-ended GPIO inputs have any particular level of impedance, and the datasheet seems to imply that any required impedance matching should be done externally.) Assuming the connection between the two GPIO pins is very low-Z, won't this current flow be essentially infinite in magnitude until one of the chips dies?
In summary, my specific questions are:
- Should I add a series resistor that holds the current flow to 8mA (max that the output GPIO can source and max that the input GPIO can sink)? If so, do I pick the value based on the maximum possible voltage difference, which would be ~3.5V in the case where one of the boards is powered down and the other is still running (3.3V + maximum possible transient + safety margin).
- What effect would adding a series resistor have on signal integrity, specifically signal rise times and slew rates? This is a single-ended, unidirectional signaling protocol, but any real world resistor is going to have some parasitic reactance baked into it (either inductive, capacitative, or both).
- Should I be doing anything to clamp the voltage on the GPIO interconnect line to 3.3V, e.g., with a Zener? Would this help or hurt my quest not to fry chips?
References that are similar but failed to truly answer my question:
- (1) Connecting SPI with two different voltage reference, (2) Can a board have two power supply circuits?, (3) DC DC Converters in Parallel for double current
- this TI whitepaper has a great discussion of power supply OR'ing with a FET controller (they recommend the TI TPS2412 and an equivalent OR'ing controller from Linear is LTC4370), but since I'm not trying to combine the two boards' 3.3V rails, ultimately that didn't seem relevant to me.
I was asked in the comments about intended bit rate for the UART. I intend to start modestly (e.g., 9600 baud), but would like to reapply the same basic design to faster and more complex scenarios like LVDS at higher (couple hundred MHz) speeds, if I can make it work. Thank you for the question.