Connecting GPIOs on two boards with independent power supplies

Question

I'm trying to design a board that will accept UART/8N1 input from another board at 3.3V. While the two boards share a common GND (obviously), they otherwise have totally independent power supplies: one is powered by USB VBUS which is regulated down to 3.3V, and the other by an AC adapter that is independently regulated down to 3.3V.

My question is this: obviously the two different 3.3V rails are not going to be at exactly equal potentials. Both have some amount of ripple, both will be experiencing load transient spikes at various times, no regulator is perfectly accurate, there are thermal de-rating effects, etc. Therefore, when connecting the GPIO output pin from the other board to the GPIO input pin on my board, do I need a current-limiting resistor in series with the signal? Do I need a low Vf diode to prevent current back flow out of my board through the GPIO?

Here is a diagram that I hope makes the situation clearer:

Both the output GPIO (on "Other Board") and the input GPIO (on "My Board") are based on similar Lattice ECP5 FPGAs, and the datasheet for this FPGA family says that IO pins can handle voltages above or below 3.3V by an absolute maximum of about 300mV or preferably no more than 165 mV under recommended operating conditions. Since the voltage regulators used on the two boards both respond to load step transients with a max of about +/-50mV and have ripple deviations of less than that, I'm not concerned that the two voltage rails will deviate substantially -- except in the case where one board is powered off completely and the other is up and running.

What I am mainly trying to understand is whether there can be current flow between an input GPIO pin and an output GPIO pin given that one board's 3.3V rail may actually be 3.25V while the other board's 3.3V rail may actually be 3.35V. It would seem to me that in this case, which is going to be happening all the time, current flow would flow from the slightly higher 3.35V voltage rail to the slightly lower 3.25V rail through the GPIO line? (I can't find anything in the datasheet that says that single-ended GPIO inputs have any particular level of impedance, and the datasheet seems to imply that any required impedance matching should be done externally.) Assuming the connection between the two GPIO pins is very low-Z, won't this current flow be essentially infinite in magnitude until one of the chips dies?

In summary, my specific questions are:

1. Should I add a series resistor that holds the current flow to 8mA (max that the output GPIO can source and max that the input GPIO can sink)? If so, do I pick the value based on the maximum possible voltage difference, which would be ~3.5V in the case where one of the boards is powered down and the other is still running (3.3V + maximum possible transient + safety margin).
2. What effect would adding a series resistor have on signal integrity, specifically signal rise times and slew rates? This is a single-ended, unidirectional signaling protocol, but any real world resistor is going to have some parasitic reactance baked into it (either inductive, capacitative, or both).
3. Should I be doing anything to clamp the voltage on the GPIO interconnect line to 3.3V, e.g., with a Zener? Would this help or hurt my quest not to fry chips?

References that are similar but failed to truly answer my question:

• (1) Connecting SPI with two different voltage reference, (2) Can a board have two power supply circuits?, (3) DC DC Converters in Parallel for double current
• this TI whitepaper has a great discussion of power supply OR'ing with a FET controller (they recommend the TI TPS2412 and an equivalent OR'ing controller from Linear is LTC4370), but since I'm not trying to combine the two boards' 3.3V rails, ultimately that didn't seem relevant to me.

I was asked in the comments about intended bit rate for the UART. I intend to start modestly (e.g., 9600 baud), but would like to reapply the same basic design to faster and more complex scenarios like LVDS at higher (couple hundred MHz) speeds, if I can make it work. Thank you for the question.

Answer 1

"Hot socketing" is the name that Lattice uses in the ECP5 datasheet and app-notes for the capability that addresses your questions.

Using the correct I/O banks, LVDS signals, and correct configuration of the internal termination rsistance, bias, and clamps, no external components are required.

Answer 2

In situations like this, I like to use an optical coupler (example) in between the two systems. The systems will remain electrically isolated, so no current will flow between them in either direction. They can have completely incompatible voltage rails, they can even have different grounds. I find them particularly useful when I don't know how the device's pins behave at system startup or when one device may have power when the other doesn't. Isolating the two systems eliminates an entire class of problems. The downside is that these couplers are primarily one-way circuits. Isolated bi-directional communication is a bit more complicated.

Answer 3

Generally speaking, as long as both boards are powered up and their power supplies are within specification for the FPGAs (e.g., ±5% or ±10%), connecting the GPIO pins directly to each other should be no problem. Inputs on a powered-up FPGA have a very high impedance, as long as the pin voltage remains within the normal operating range.

But if you want to have one board powered and the other not, then you'll have to take precautions. In particular, it's possible that the "other board" may try to drive a logic high signal into an unpowered input on "my board". This would drive current through the protection diodes on "my board" into its power supply rail, and this may have undesirable effects. (And vice-versa, of course.)

You can establish protocols to prevent this issue. For example, you could require that the GPIOs on "other board" are tristated or driven low before power is removed from "my board". But if that can't be guaranteed, then yes, some current-limiting series resistors might be called for.

Answer 4

You should check the datasheets for the max/min values of one FPGA's output, vs the other's acceptable input range. Generally speaking, you can connect two logic devices that are both 3v3 logic together. While there might be a 0.05V difference between the rails, the input of an FPGA is relatively high impedance, so whether your logic is 3.3V or 3.35V represents a tremendously small amount of current difference.

You could check the other data sheets, and see what values come up with. If both FPGAs are ECP5 then there's likely no problem. For instance, the maximum input for one of the 3.3V logic groups LVCMOS33 is 3.465V, the maximum output is Vlogic - 0.27V. Given that the maximum allowed value for Vlogic is 3.465V, there's no way for one FPGA to generate too high and output voltage for the other to use as an input.

Dave points out that there is a case for one FPGA not booting properly if its input pins are driven. You need to read the datasheet and check if this is a problem, which may call for a buffer or similar, or a code fix. Again the datasheet will tell you for definite whether the input needs to be tri-stated, strapped, or whatever at boot.

You could add a small series resistor to limit the current, but this would likely have no effect. A Zener again would be unlikely to do anything. This particular instance calls for a good thorough read of the datasheets.