I have been working on a data acquisition system that requires fairly high sample rates given the resolution and dynamic range requirements. The front end performs well, but to avoid wasting large amounts of production excess, I am trying to shoehorn a solution here that uses an STM32F446 microcontroller in lieu of an FPGA or beefier MCU/CPU. I have an implementation on a Lattice FPGA and on an Altera MAX10 that work beautifully, but oohhh that darn chip shortage is still crampn' our style eh? The system will have a pretty large number of RTOS threads running doing housekeeping, communications, and a good number of other things requiring tight timing, and some other squirrely demon magic, so my thought here is to add some external hardware and try to leverage the peripherals in the MCU as much as possible to avoid CPU intervention. This function will be using one of those fancy SAR ADCs from Linear/Analog that includes an internal FIR filter.
Here is the timing diagram I made for the idea:
The basic idea is to use the I2S or SAI peripheral in asynchronous slave mode to receive data from the ADC as it is clocked from a timer instead of the Serial Communication Peripheral(s). This will allow for a few things in my mind, it will avoid the funky 16b transfer per DMA request "feature" of this STM32 family, it will allow for a maximum of 32b per transfer from the ADC given the RX FIFO or RX Data register sizes of the I2S or SAI in PCM/PCM-Like Modes, and given the timers on this part, they should be able to run in a pretty tight fashion. I still need to do some more research in the device errata and timing specifications fwiw.
TIMA will be clocked from an external source or internal PLL to generate a clock signal that will be used both as a synchronization signal for the ADC input conversion clock and the ADC output data ready flag through some clocked d-flipflops as well as the Serial Clock. TIMB will be clocked from the falling edges of the data ready signal post flip-flop, and have an output compare channel configured to generate an edge after N-Pulses of the data ready signal. This will allow for adjustable over sampling ratios on the ADC data given the LTC2380-24 ADC operation. Once N conversions have been confirmed, the reset of TIMB will start TIMC in a one-shot down count mode as it is clocked by the synchronization clock signal. The initial counter value of TIMC will determine the number of bits to be shifted out of the ADC. TIMC will have an output compare channel configured to stay at a logical-1 while the down-count of TIMC is above zero. The TIMc_OCCx signal and the synchronization clock will be connected externally with an AND gate of the timing proper variety and the AND'ed output will now become the Serial Clock signal sent to the ADC and the I2C/SAI data-clock in parallel. If all is well, then the serial data output of the ADC will then be received in this state and be ready for a peripheral-to-memory DMA transfer upon receiving the complete data frame, then consumed by the data processing task using a circular buffer, either through DMA auto incremented transfers or just in software since at this point the timing is no longer critical.
Im poking around here since I have not seen someone online doing something similar with these MCUs and I'm wondering if someone has had a good/bad experience in doing something like this, with the STM32F4 family of MCUs in particular. My biggest concern is the undocumented maximum asynchronous slave rx clock frequency for the SAI or I2S peripherals in the reference manual or datasheet. There are some timing specs in the datasheet that lead me to believe that this should be fine, but the peripheral documentation is a little light on specifics for this operating mode. Until I can get back in the lab I'm getting this running with qEMU and some behavioral mocks, so any experience is appreciated!
