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An MCU GPIO's slew rates may be increased, or decreased, and this allows setting the maximum GPIO switching speed. But how is it implemented on hardware level?

I know that those outputs are implemented with the use of FETs, and their "switching" speeds are constant values not depending on current, as it is the case with BJTs, so the option to increase current is not on the table. How come we have 2, 3, 4 voltage frequency modes for a GPIO? Are different output circuits implemented for different frequency modes for the same pin?

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  • \$\begingroup\$ Your question isn't really clear to me. There is a maximum guaranteed slew rate for an I/O pin, given a specific load type. That's usually in the specs somewhere. GPIO is usually FET-based, not BJT-based, these days. The rest of what you write mostly confuses me. So I'd appreciate some further effort to clarify the question. Others may differ on that. But that's where I'm at. \$\endgroup\$
    – periblepsis
    Commented Oct 29, 2023 at 14:50
  • \$\begingroup\$ The answer Slew Rate Adjustability is for using discrete FETs, and says the slew rate can be controlled by adjusting the current used to charge or discharge the FET gate. Not sure if a MCU GPIO slew rate can be controlled in the same way. \$\endgroup\$
    – Chester Gillon
    Commented Oct 29, 2023 at 14:58
  • \$\begingroup\$ @periblepsis Sure, I im perplexed by the fact that a circuitry (let's call it a driver) consisting of 2 FETs supports up to 4 frequency modes, and the reason for my confusion was that we are unable to change FET characteristics by, say, increasing current. And if that is the case, how come a single driver with constant switching speed we cannot change supports up to 4 frequency modes? The hypothesis was that 2 or more drivers were used, but I could not find a single mentioning of that in any of the datasheets I'd happened to lay my hands on. \$\endgroup\$
    – Dmitry Murashov
    Commented Oct 30, 2023 at 19:13

1 Answer 1

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Mostly, the slew rate for GPIOs is increased by adding more drivers in parallel like the one shown below.

enter image description here

I have shown above an image of a GPIO that has 2 drivers. Each has an independent enable as shown. When frequency of the data is low, we would set EN1 = 1 and EN2 = 0. This will tri-state the bottom driver and keep only the top one enabled. So, drive strength will be lower and hence slew rate will be lower.

When frequency of the data is high, we would set EN1 = EN2 = 1. This will ensure maximum drive strength for the GPIO and for the same given cap load on the OUT pin, the rise time and fall time will reduce thereby increasing slew rate.

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  • \$\begingroup\$ Doesn't data flow with EN1 = EN2 = 1 require the push-pull buffers as well as pre-divers to be perfectly synced? How are these discrete blocks guaranteed to sink/source right at the same time? Making transistors pretty much identical at the chip level might be possible to some extent but we are talking about reducing nanoseconds by nanoseconds. Can you provide a source for this implementation? \$\endgroup\$
    – Rohat Kılıç
    Commented Oct 29, 2023 at 17:46
  • \$\begingroup\$ @RohatKılıç The transistors that drive the pins are large and relatively slow. The logic controlling them is much faster. Sync at the subnanosecond level is not difficult. \$\endgroup\$
    – John Doty
    Commented Oct 30, 2023 at 0:35
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    \$\begingroup\$ @RohatKılıç, the delay difference between the pre-drivers is quite small when compared to the rise, fall times of the waveform on the pad. So, the mismatch does not significantly affect the output rise, fall times. The mismatches do cause some crow-bar current but, because it will be for a very short duration, the average current is not too high. We could use break-before-make control to avoid it. This GPIO architecture is very common. Refer for example to page 39-44 rc.library.uta.edu/uta-ir/bitstream/handle/10106/24772/… \$\endgroup\$
    – sai
    Commented Oct 30, 2023 at 7:39
  • \$\begingroup\$ @sai thanks. Very useful. \$\endgroup\$
    – Rohat Kılıç
    Commented Oct 30, 2023 at 8:10
  • \$\begingroup\$ That explains it perfectly, thanks! @RohatKılıç Thanks for the reference! \$\endgroup\$
    – Dmitry Murashov
    Commented Oct 30, 2023 at 19:17

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