# Is it possible to know through simulation whether we have the right number of decoupling capacitors?

More decoupling capacitors than a certain amount does not improve the power integrity much. I am not sure if this is a case of diminishing returns or a case of reaching a wall.

How exactly can we carry out a simulation and know if the decoupling capacitors are enough and the right value and in the right locations?

This question is specifically about large FPGAs that have a whole lot of voltage domains and clock domains.

• Given that in the real world, most things eventually boil down to probability, rather than absolutes, I wonder if it is truly possible to answer this without also defining an acceptable failure rate for your design. I imagine that the approach taken to the problem would be different for a piece of aircraft electronics critical for flight safety, from that for a piece of consumer hifi. Commented Oct 30, 2023 at 13:02

I basically agree with Justme but already started writing so here is my answer:

The short answer is yes, it is possible to determine this via simulation but determining the parasitic values to actually pull it off can be very challenging.

I see decoupling capacitors as having two major roles:

• Keeping switching noise at the switching device. From an EMI perspective, high current, high frequency spikes along a power trace can be very noisy. The capacitor acts like a charge resevoir and filter.
• Compensate for high routing impedance from the power supply to the switches to enable faster switching.
• The PCB routes from the power supply to the device and the device package pins both provide parasitic resistance and inductance which limit switching current. Decoupling capacitors work because typically L_pin <<< L_PCB

For FPGAs, the latter is usually the main objective. To achieve it, decoupling capacitor size, count, placement, etc. depends on the parasitics that the capacitors are meant to compensate for.

Determining these parasitics and how they interact for simulation purposes can be very challenging but some tools can help:

• A regular SPICE simulator. Bonus if it has S-parameter support.
• Signal integrity simulators (typically also do power integrity)
• Full EM simulators which support discrete device models (if you are motivated enough, bonus voltage distribution and possibly thermals)
• ANSYS HFSS
• FPGA Vendor Tools (essential to determine where current is actually consumed and how much current is consumed, ASIC internal power distribution can be non-obvious)

Depending on the tools, the workflow may include:

1. Calculate the parasitics by hand
2. Setup the tools
3. Collect simulation models for discrete parts
4. Port design to simulation tool
5. Generate simulation models from layout ("parasitic extraction")
6. Run simulation
7. Iterate

From experience, it is not worth doing this detailed analysis work for small, low cost designs. This design process has some non obvious costs such as:

• Engineering time
• Compute time - these simulations can become large
• Software cost
• Simulation flow setup time - high initial cost if not already done
• Modeling costs for custom parts
• Risk (i.e. "re-spin cost") associated with inaccurate part models
• Getting accurate high frequency models for components can be a major challenge.
• Some companies offer excellent support for this. Murata offers SPICE and S-parameter models and some semiconductor companies provide IBIS models for high speed transceiver simulations.
• Some companies outsource modelling to companies like Modelithics
• Some companies offer no models but comprehensive data in datasheets. Data entry to custom models is not too hard but is error prone and time consuming.
• Some companies offer very little good data.
• If you want to fully rely on your simulation, you may end up limiting your self to a handful of companies (which have models) and this can cripple a supply chain or design flexibility.
• A workaround is to only use parts targeting RF applications. These almost always have models available. However, these are typically too expensive and have unnecessarily good performance for a PDN.
• Another workaround is to assume that similar devices will have identical performance between manufacturers. Then use models from a manufacturer that offers them. This can work decently for generic (not low ESL) ceramic capacitors but provides no guarantees.
• Risk (i.e. "re-spin cost") associated with inaccurate PCB models
• This is where the dedicated simulation tools mentioned are very useful: they extract the PCB parasitics for you directly from the layout.
• However, from experience, these parasitics can lack accuracy and be sensitive to the full PCB stackup. This generally needs to be fully characterized with a manufacturer. For example, PCB weave and PCB prepreg often get summarized as a specific material loss.
• Risk of inaccurate FPGA load info due to incomplete or changing firmware

These costs may worth it for bleeding edge designs (ASICs, hybrids, HDI, designs with very costly SoCs, reliablity qualified designs).

The lack of part models and the challenges in PCB modelling typically drive me away from fully accurate simulation and towards following rules of thumb, building a prototype, and testing. The costs here are more obvious and include parts+material+manufacturing+shipping time+test time at given quantity.

Some guidance for the "rules of thumb":

• I did not expect that simple question would have a complex answer. I had assumed that since we have so much around for signal integrity, it must be possible to get reliable data for power integrity as well after following some set formula. But like you said, if the manufacturer does not give us what we need then it is not possible to do signal integrity or power integrity simulation. Commented Oct 30, 2023 at 17:36

Yes, it is possible, in theory at least. In practice, difficult.

It requires that the simulation software needs to know about the FPGA current consumption, for which it needs to know what logic the FPGA runs and what internal blocks such as PLLs are enabled and at what frequency each block is clocked at.

So, rather than simulate it, the FPGA vendor gives you a ballpark approximation about what kind of bypassing you need so that the FPGA works in all cases, under full loading. So you likely don't need that much bypassing, but it is difficult to estimate.

In more complex cases where you really need to analyze the system, you are given the power delivery network specs it must handle - i.e. how much DC current, how much AC ripple voltage and current, and the graph about impedance you need to provide at different frequencies.

Then you can start simulating the PCB design, the stray capacitance and inductance of the PCB traces and where some capacitance would be most useful - taking capacitor properties such as ESR and ESL into consideration, in addition to their other properties and quirks like capacitance being dependent on applied voltage. So it really requires to know how e.g. MLCC capacitors start to behave when you go up or down in package size or go up or down in the rated voltage, or temperature etc.

• ok, this seems to be atleast 1000 times more difficult than I can imagine. I read somewhere that the decoupling capacitor performance depends on the clock frequency of the device since that will decide the frequency at which it switches and needs to be supplied current. So, how can the vendor give a table and expect that to just work, implying that it will work across all frequency ranges? Commented Oct 29, 2023 at 21:53
• @quantum231 A square wave (clock or other) is not just one frequency (see Fourier Series). Decoupling capacitors try and filter as much high frequency current as possible directly at the device pin since the PCB may not be able to provide that current through its power delivery network (maybe just one high impedance trace). On the other hand, very high frequency signals may not even make it out of the device package. ASICs typically have on-die decoupling too. Decoupling is generally a matter of PCB and package parasitics.
– maxp
Commented Oct 29, 2023 at 22:10
• Surely we also need to know the tolerance of the circuit? Commented Oct 30, 2023 at 17:30

Yes, it is possible I usually use a spice package, but the real world parasitics in components and traces need to be estimated well and then a spice package can be used to simulate the circuit. Each trace has inductance, you can use a pcb trace calculator to estimate the inductance and resistance of the copper traces. The load will also need to be characterized well such as AC response and max current draw. In addition the AC response of the voltage regulator needs to be characterized.

A package like LT spice also has real world capacitors that have the ESR's and ESL's built in. Parallel the capacitors and add in the traces as necessary. This will give a good enough result to get you 90% of the way there in most cases. If the design is area constrained use XY 3 terminal caps to reduce ESL.

simulate this circuit – Schematic created using CircuitLab

• For OP's use case, where the load is an FPGA, you probably want the load to be a current sink rather than a resistor. Then the challenge is figuring out what current waveform it needs to produce to reasonably model the actual circuit. Commented Oct 31, 2023 at 1:50
• I agree, I usually do a voltage dependent variable resistor in lt spice Commented Oct 31, 2023 at 2:18