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I'm currently designing a register where there needs to exist a data input pin (DIN), Clock (CLK), Reset (RST), and a RUN pin. The register is designed such that, only at positive edges of the clock signal:

RUN RST Functionality
X 1 Resets value in register to 0
1 0 Register allows for change in value
0 0 Register does not allow for change in value

As seen in the table, RST does not depend on the value of RUN to perform its function (which is to reset the value in the register to 0). RUN simply pauses any change in value.

As of now, my design involves using a D flip-flop structure and a MUX, and all the functionality works apart from RST. RST only works when RUN = 1. When the system is paused (RUN = 0), the RST pin has no effect. I've tried other designs, and it's been messing with me. Is it this hard to implement a D flip-flop with synchronous reset and an enable (RUN) pin?

Any guidance in the right direction would be greatly appreciated.

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2 Answers 2

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You could add a 2nd mux as shown in the diagram below (MUX2):

schematic

simulate this circuit – Schematic created using CircuitLab

MUX1 has precedence. When RST=1, it synchronously resets the DFF (REG1) to 0.

When RST=0, MUX2 comes into play. When RUN=1, the input data is captured; otherwise, the DFF retains its previous state.

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  • \$\begingroup\$ Damn. This was so genius it made me feel stupid. Thank you so much! You won a fan. \$\endgroup\$ Commented Nov 1, 2023 at 19:57
  • \$\begingroup\$ But for future reference, is there ever a practical realisation where this is a probable solution? Would designs like this face issues in practicality, or is it more common than I think? \$\endgroup\$ Commented Nov 1, 2023 at 19:58
  • \$\begingroup\$ @RizqiBusiness: You're welcome. I'm glad to help. This is very common, and I see no issues since you are keeping everything synchronous. \$\endgroup\$
    – toolic
    Commented Nov 1, 2023 at 20:09
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You can try with a CD4013B dual D-Flip Flop (or equivalent) and a AND gate. The AND gate acts as a clock inhibit when RUN is low. The RES (reset) pin puts the output low when pulled high and SET is low.

schematic

simulate this circuit – Schematic created using CircuitLab

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  • \$\begingroup\$ What do you mean by synchronous reset? \$\endgroup\$
    – Fredled
    Commented Oct 31, 2023 at 21:45
  • \$\begingroup\$ Yep, I tried designs similar to these but could never get them to be clocked. Thanks for the response however. \$\endgroup\$ Commented Nov 1, 2023 at 19:59
  • \$\begingroup\$ toolic The have the reset at the rise of the clock doesn't make sens since it should inhibit the clock to have an effect. Another way would be to force the D pin to be at a certain value. There are several logic gates and logic ic to do almost everything. \$\endgroup\$
    – Fredled
    Commented Nov 1, 2023 at 20:40

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