# Synchronous buck converter using gate driver IC

I designed synch. buck converter by using gate driver, MOSFETs, inductor and capacitors. I am currently testing in open-loop configuration and later I will test in closed-loop with microcontroller as a feedback. Please see below for scope images and schematic. My question is that why am I seeing some discrepancies between measurement and expected value of output? When I set duty cycle 50% and fsw = 20 kHz, I expected output to be around 7.5 V and 100 mA with the load of 75 Ω. But I had to increase duty cycle to 62% to achieve my expected value. Is this somewhat expected result? I see output voltage as I expected without any load. But when there is load, discrepancies starts to appearing. Also how do I decrease the spike at the switching node?

Following is my design parameters:

1. Vin = 15 V
2. Vout = 7.5 V
3. Load fixed = 75 Ω
4. Iout = 100 mA
5. Duty cycle = 50%
6. fsw = 20 kHz
7. Inductor = 10mH
8. Output capacitors = 6.6 uF
9. Ripple current = 20%

Open loop testing without load (fsw = 20 kHz, duty = 50%):

1. Yellow = output voltage at the capacitor
2. Blue = Vgs of upper MOSFET
3. Green = vgus of lower MOSFET

Open loop testing with 75 Ω (fsw = 20kHz, duty = 50%):

1. Yellow = output voltage at the capacitor
2. Red= inductor current

Open loop testing with 75 Ω (fsw = 20 kHz, duty = 62%):

1. Yellow = output voltage at the capacitor
2. Red= inductor current

Switch node spike:

1. Yellow = voltage at the switching node before inductor
2. Red = inductor current

Schematic

• I've reverted the last edit to this question as it deleted essential context for understanding the question and its answers. Nov 3, 2023 at 15:44

If a buck converter worked according to Vout = Vin*duty cycle (continuous mode) without a control loop, there wouldn't be a need for a control loop at all.

In reality, the switches have resistance as do the inductor and PCB traces. The PWM has dead time between the lower and upper FET gates.

The source has finite impedance as well. Those things will cause voltage drops as your load current increases, which is the reason that we use a control loop to adjust the duty cycle to keep the output voltage constant.

• Hi John, thanks for clarification. Understood. I will see how it works in a closed loop with mcu. Btw, what is causing that spike at the switching node(L1.1)? I included image right above the schematic image. Is this because upper fet is driving too fast? Nov 1, 2023 at 17:01
• Looks like you're turning on the high side FET while the low side body diode is conducting due to the dead time. At that point there will be a short high-current spike to provide recovery charge to the diode. That causes ringing due to the parasitic inductance and capacitance in the circuit. The spike on the inductor current is probably not real, it's probably coupling into your current probe. In any case it's fairly normal behavior. Nov 1, 2023 at 17:10
• Okay thanks John. So do you say that open loop testing result is somewhat reasonable measurement? This is my first time designing this kind of circuit in PCB and I wanted to learn if there were any mistaken. Thanks again. Nov 1, 2023 at 18:27
• @K.Son Yes, it looks reasonable to me. Nov 1, 2023 at 19:11

Why am I seeing some discrepancies between measurement and expected value of output? When I set duty cycle 50% and fsw = 20kHz, I expected output to be around 7.5V and 100mA with the load of 75 ohm. But I had to increase duty cycle to 62% to achieve my expected value

A synchronous buck converter can be relied upon for producing the right output voltage on light to moderate loads (without feedback) providing all the below are true: -

• The input supply voltage remains stable
• The switching MOSFETs have a much lower on resistance compared to the most demanding load
• The inductor's DC resistance is also very low compared to the most demanding load
• You use a PCB and have a decent/sensible layout
• You use a sensible valued output capacitor

If you don't provide the above, the output voltage will sag below the theoretical value and, to compensate, you'll need to increase the duty-cycle.

• I wonder why the downvote without any comment? As far as I can see both answers are correct, so I'm upvoting this one to compensate. Nov 2, 2023 at 15:21