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Recently I'm working on a project that involves a FPGA and two high precision DACs. The DACs require a low jitter 27MHz clock (RMS jitter < 1ps) to function at their datasheet performance. There is currently a low jitter oscillator on the PCB, which will be used as the main clock source for the FPGA and the DACs. However, I'm not really sure about how I should route the clock signal to these chips.

I have three plans:

  1. Fanout the clock on PCB without a low jitter clock buffer. I'm not sure whether doing so would degrade the clock signal due to high load on the clock trace and reflections from multiple devices. If the answer is NO, how should I do it properly?
  2. Fanout the clock on PCB with a low jitter clock buffer. This definitely should work, BUT the problem is that we are developing a portable device so that we don't really want to add unnecessary large components. The FPGA, the DACs, and the low noise LDOs already occupy a lot of space.
  3. Fanout the clock using the FPGA. This means connecting the oscillator to one of the CLK ports of the FPGA, and also connecting the CLK port of the DACs to the FPGA's PLL ports (although they are designed specifically for PLL outputs, PLL ports are the only dedicated clock output ports on the FPGA, so I guess these pins have the lowest jitter possible). Then, use assign dac_clk = xtal_clk; to directly connnect them together. I don't know if this would introduce extra jitter because I have no idea about how this kind of direct pin-to-pin assign is physically implemented on the device (I think the signal would at least passthrough the IO cells of the FPGA, and I guess these cells may introduce jitter). The FPGA we use is Intel MAX 10 series, a low-end non-volatile FPGA for cost-sensitive applications, so I'm also not sure about whether the global clock networks of this FPGA is stable enough.

Which one should I use? Are there better ways to do this? Many thanks for your ideas and opinions. :)

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    \$\begingroup\$ What is the signalling standard you use for the clocks? LVDS/PECL/CMOS/etc.? How many DACs? \$\endgroup\$ Nov 2, 2023 at 10:42

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Answering your questions in order:

  1. Whether or not you can fan out directly without a buffer will depend in signalling standard used for the clock, and the number of devices you are connecting to.

    • For single ended, you could probably get away with fanning out directly if there are only a small number of loads (maybe 4-8, depends on signal standard). I would either use separate traces for each device (not ideal), or a tree-style routing, possibly with power splitters if you have a fixed impedance trace (better). In each case you want to keep the trace lengths equal to minimise skew between your devices as much as anything.

      If using individual traces, splitting right at the source so as to minimise reflections at the split may work OK. Keep each trace the same length and same characteristic impedance and you may just about get away with it.

      For the tree style routing, you basically split the trace in two, then later on split each trace again, and so on. You commonly see these sorts of power splitters in RF applications - see "Wilkinson Power Divider". Given your 27MHz though, these would be physically very large (over 2cm each split), but would give very nice results.

      If you don't have a set characteristic impedance, and not too many splits, then you can still use the tree approach without true power dividers. You just double the impedance after the split. So if you start with a 50 ohm microstrip from the clock source, after the split you run two 100 ohm microstrips (2 clocks). Each of these then splits into two 200 ohm microstrips (4 clocks). Splitting again you get 400 ohm and 8 clocks. At some point the impedance will become too high to be useful.

    • For differential signalling, I wouldn't even consider splitting without a buffer. If for no other reason that it would be physically very difficult to route - you'd have to split through via pairs on different layers.

  2. Clock distribution buffers are very nice for this sort of thing - it's precisely what they were designed for. You can get some very nice low jitter buffers that fit in a 4x4mm or 5x5mm QFN package with no other parts required (beyond a decoupling cap on the supply rail, and in some cases maybe termination resistors if not built in). This will give the best results for differential signals.

  3. Using the FPGA as a fan out buffer would be a poor choice. The jitter induced by the IO buffers would be far too high for precision sampling applications. FPGAs are geared more for receiving clocks than transmitting them, and while some have dedicated clock outputs which should be ok, they are generally few and far between.

    To give a real world example, we tried this using a Stratix V. In the design we had a clock come in (at maybe 2-3ps RMS jitter, wasn't uber clean), and then fed it back out to two converter devices through standard IO pins (DDIO blocks). The signals that came out had 15-20ps RMS jitter. Was just about ok for our application, but not great. Our current designs have moved away from that approach.

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  • \$\begingroup\$ OMG thanks for the information! This really helps me a lot. I'm using a single-ended oscillator, so I think I would go with the tree branching layout. :) This is the first time I use StackExchange. I'm so glad that I can receive this kind of high quality response. \$\endgroup\$
    – XDflight
    Nov 2, 2023 at 15:11

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