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I have a PCIe clock buffer with 4 outputs that I would like to use for more than 4 PCIe devices. My question is can I daisy chain the buffers such that one buffer output is the input to the next buffer. granting me 7 clock differential pairs? enter image description here

From my research, for example the answers to this question, I gather that a phase shift from the buffer delay to the clock signal should be compensated when timing is recovered from the PCIe differential pairs. Is there anything in my understanding I am missing to be able to say yes, the daisy chain clock buffers should work?

Thank you!

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It's possible to daisy-chain PCIe clocks. Each buffer should be 'zero skew', that is, the outputs should align closely with the input.

However, even if the skew is zero (or close to it), the daisy-chained stage could have some additive jitter, which is something to be mindful of as your clocks need to meet the system jitter and skew requirements set out for the version of PCIe you intend to support (e.g., Gen3 or Gen4.)

That said, if you're in the design phase it's better to choose a clock buffer that has enough outputs rather than cascade them. Then you only have to concern yourself with just the one clock layer.

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  • \$\begingroup\$ Thank you for the 'zero skew' key word. I will keep trying to find a buffer with more than 4 outputs that meet my tight rating and sourcing requirements, but I wanted to ask this question anyway to study the concept. I will look out for the skew and jitter parameters. Thanks! \$\endgroup\$
    – ztan
    Nov 3, 2023 at 17:27
  • \$\begingroup\$ Renesas (nee IDT) has a great selection of clock buffers. Here's one that has 8 outputs and is rated for Gen3: renesas.com/us/en/products/clocks-timing/… Also check Diodes Inc and TI. \$\endgroup\$ Nov 3, 2023 at 18:14
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Use of the reference clock is optional, and a lot of designs don't even use it at all. The PCIe protocol can compensate for a frequency offset by inserting and deleting symbols.

In any case, the clock significantly slower than any other signals on PCIe, so it will be multiplied in a PLL, and there is no useful definition of a phase relationship between the refclock and the data lanes.

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  • \$\begingroup\$ A bit misleading there. All PC motherboards provide REFCLK, and it's more the exception than the rule that a peripheral doesn't require it. \$\endgroup\$ Nov 2, 2023 at 23:12

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