# Detect “real” overcurrent/short-circuits vs. current peaks

We have a MOSFET that drives a load. The load has a sense resistor in its current path and its voltage is used to trigger a circuit that can disconnect the load if we detect an over current condition.
But it wasn't that easy. Many kinds of loads generate large pulses when connected (input capacitors, etc), so temporal overcurrents can actually trigger the latch, so we fed that current sense voltage into a capacitor. It looks like this:

The issue is that higher currents will kill the MOSFET (and other existing circuitry) exponentially faster, while higher voltages (from the current sense) will change the capacitor less than linearly faster.
If we tweak the value for a reasonable current/time to trigger the latch, a higher current will take too long, while tuning for a high current will overshoot at lower currents.

We have been thinking about using a thermistor instead of a capacitor (right response curve) but they all seem to be too slow for our case (at 200A we have about 40us to shut off). Now there's an idea of using an integrator op-amp to measure current*time...
Does any of that make sense? Is there a industry standard practice for this sort of case? This can't really be this complicated, it feels like it should be a common issue... can it? Isn't it? :)

Our issue is not about the components (whether the op-amp will be able to drive the MOSFET at X Amps), it is about triggering in 'this is too high too long' rather than on 'high current but short and okay' situations. I've removed the device names accordingly :)

• Seems you want -two- time constants, one about 40us, one much slower. You want to mimic the thermal model of the MOSFET die temperature. The fast time constant is how fast the die temperature rises, the slow one is how fast the case temperature rises. – Bobbi Bennett May 9 '13 at 22:08
• @BobbiBennett: Absolutely, but what's the best way to model that? A capacitor? A PTC? An integrator?... – Rodrigo Lopez May 10 '13 at 13:33
• -1 you seem to be discounting a bunch of theories yet you are persisting in showing the op-amps in the circuit and to distract people from looking at the circuit you have removed ic references and part numbers. Just how relevant is the circuit to your experiments. If not relevant then get rid of it and explain what your circuit is that is having troubles. – Andy aka May 10 '13 at 17:40
• @Andyaka This is exactly the circuit that we have. The part numbers were not helping focusing the conversation. We don't have any issue with the parts, if the circuit decides to cutoff it does cut as you'd expect. We have an issue with the decision itself. As in, how do build a model that triggers on the right event (integrate? charge capacitor? PTC? mix?) – Rodrigo Lopez May 10 '13 at 19:35

The underlying problem description suggests a possibility of a low-tech solution rather than the high tech path. This is not to say that the mentioned integrator based approach won't work, of course.

Basically, how about two current limiting mechanisms in series:

• One that works well within the 40 microsecond time, but triggered only at close to the absolute maximum current rating for the affected components. This would have a sharp threshold, no RC or other integration involved, but would be auto-reset - the equivalent of a fast PPTC, from a circuit block perspective.
• One that integrates threshold over time, either using an RC or an op-amp integration - hence it has a time constant potentially longer than the 40 microsecond limit. The threshold would be much lower than abs-max: Set it for the desired sustained-current limit.

This way, impulse currents such as for capacitor charging at start-up would get through, so long as they are under abs-max, while "slow-fuse" overcurrent protection would be in place for normal operating conditions.

• This is actually what we have right now, currents up to 45A can take up to a number of ms, after 45 they can take only a number of us. If the low ends at 45A and the "high short" triggers after that there will be 45.01 currents allowed only for us. If the "high" starts later (say at 100) there will be a span (45...100) where the non-linearity of the capacitor will bite :) – Rodrigo Lopez May 10 '13 at 13:23
• @RodrigoLopez If you're integrating for the operating current trap, then either a higher current or a longer duration will trigger the cut-off. In other words, say 5 mS for 46 Amps, but just 0.5 mS for 60 Amps. If you need finer linearity than that, you'd have to incorporate a fast microcontroller reading an ADC and controlling the current switch: That way you can map the entire time-domain behavior. – Anindo Ghosh May 10 '13 at 13:50
• Aboslutely, I imagine a local MCU in the way to go later on, for now we just wanted a simple (heh) analog solution. The second part of your answer is what we are trying next! :) – Rodrigo Lopez May 10 '13 at 14:37

Rather than using a current sensing resistor, I would suggest that you instead monitor the voltage drop across the MOSFET and compare it with a reference signal that indicates how much the MOSFET is allowed to be dropping at any given time. When the MOSFET is not enabled, it should be allowed to drop the full supply voltage (indeed, that would be expected). Once it is enabled, its voltage drop should fall fairly rapidly, though exactly how rapidly will depend upon the nature of the load to which it is connected. If the voltage drop on the MOSFET doesn't follow something resembling the proper profile, that would indicate a problem and should trigger a system shutdown.

• We did have this sort of setup (using the MOSFET), but we do have the current sense there anyway (there's a MCU logging things too) The second part of your answer hits the nail, but "a proper profile" is what is difficult to get, and where the capacitor is not cutting it. – Rodrigo Lopez May 10 '13 at 13:26
• @RodrigoLopez: It may be good to have the MCU log both the current and the MOSFET voltage drop. It may be helpful to use a combination of high-pass and low-pass filtering on MOSFET voltage-drop signal; the signal feeding into the low-pass filter should be "blanked" so that when the MOSFET is off it reads as zero rather than maximum, but the high-pass filter signal should not be blanked (since unblanking it would otherwise cause a massive spike). – supercat May 10 '13 at 14:48
• Absolutely, the MCU is not awake all the time though. That's why the analog modelling the power buildup is necessary. – Rodrigo Lopez May 10 '13 at 14:51
• @RodrigoLopez: If the MOSFET has secondary thermal protection, and if the circuit is supposed to operate continuously under non-fault conditions, I wouldn't expect the over-current shutoff would have to be particularly precise. The biggest requirement would be to ensure shutdown under conditions that would be so grossly overloaded as to melt the device before a temperature safety could trip. – supercat May 10 '13 at 14:54
• @RodrigoLopez: Hardware to shut things down under gross overcurrent conditions is a good idea, certainly. Even if the CPU is merely logging stuff, though, keeping track of the voltage drop as well as current may be helpful (e.g. if because of aging or temperature, it takes longer for the voltage drop to approach zero even with normal current levels, that could be good to know). – supercat May 10 '13 at 14:56

I agree with others that you should have a MOSFET gate driver between the gate and IC2B. A very slow gate turn-on with heavy drain current can cause you significant turn-on loss, since the switch is not saturating quickly. A very slow gate turn-off negates any attempt to do a 'fast' overload shutdown, since the gate capacitance will take a finite amount of time to discharge (not to mention power dissipation during the slow turn-off).

I really suggest using a MOSFET driver IC, one that has several amps of turn-on and turn-off capability. If you don't want to go down this route, you can at least implement a fast turn-off using a PNP transistor and a diode and see if it gains you anything.

simulate this circuit – Schematic created using CircuitLab

You really need to figure out if switching loss (slow turn-on and turn-off) or conduction loss ($I^2 \cdot R$) is what's killing you. If it's conduction loss, you could parallel the MOSFETs for more power handling capability. If it's switching loss, improve the gate drive.

• Nothing is killing us, really. It is not that any of the parts doesn't do the job, it is just that we don't have a good timing model. We do use drivers in other parts of the circuit :) – Rodrigo Lopez May 10 '13 at 13:30

I've never done this. But I think I understand your question, you want to have suitable response times for both fast high current and moderate over current conditions.

Well, the first compromise in your model is power vs current. The heat going into the chip is I^2, but you are measuring just I. But you don't need precision, just good limits, so here is a simple 2 tau circuit:

simulate this circuit – Schematic created using CircuitLab

I pulled the resistor and capacitor values out of my hasty hat, you will want to tweak them to the desired response.