I am challenging myself at understanding my integrated amp's MM/MC phono stage; The amp is a Rega Elicit mk. I. It is a somewhat complex design and as a hobbyist I'm out of my league. The circuit looks a bit like an op-amp built out of discrete parts, so I have taken the typical op-amp block diagram as an inspiration and color-coded the sub-circuits I think I recognize but I'm not certain of anything except the constant-current sources and sinks as I recognize their LED voltage references.

Sorry for the poor image quality, the amp is more than 30 years old and all I have are those scans of the schematics (They're not even of the right board revision but are close enough). Image taken out of Hi-Fi Engine Library : https://www.hifiengine.com/hfe_downloads/index.php?rega/rega_elicit_schematics.pdf enter image description here Below are the block outline legend:

  • Blue: Darlington pair emitter follower current buffers
  • Red: Constant current sources and sinks
  • Brown: Cascaded emitter follower/common base differential input stage
  • Green: Level shifter
  • Cyan: Class AB output stages
  • Orange: Long-tail pair diffential amplifiers with constant current sources and current mirror active loads performing single-ended to push-pull conversion
  • Gray: Unknown configuration...

I would appreciate any help in correctly identifying the sections and type of the building blocks so I can study each sub-circuit in depth. I am in the process of porting the schematic into LTSpice but I see no point in trying to analyse a simulation if I don't understand the basics first.

I have also a couple unresolved interrogations:

  • Why use multiple transistors in parallel for each half-phase of the input? I would guess to lower the output impedance and possibly "swamp" any Hfe variations?
  • How is the RIAA equalization performed?

Many thanks in advance.

  • 1
    \$\begingroup\$ Site rules require you to give attribution to the image source. Add it to the question - not in the comments. Thanks. It wouldn't do any harm to specify the make and model too. \$\endgroup\$
    – Transistor
    Nov 4, 2023 at 21:26
  • \$\begingroup\$ You might try sectioning into two separate amplifiers. The first complete amplifier has output at TP14. The second complete amplifier starts at R?99 with output at TP12. \$\endgroup\$
    – glen_geek
    Nov 5, 2023 at 1:39

1 Answer 1


Paralleling input transistors is done to reduce noise as described by Leach here.

The RIAA equalization will be some RC networks, possibly the ones to the right of the first bias diodes, and to the left of the second bias diodes. You can look at those and see if the time constants look reasonable for RIAA.

  • \$\begingroup\$ Thanks for the link to the noise reduction paper. Regarding RIAA eq, R220 (2k4) and C77 (33nF) do look like a low-pass filter and the time constant is very close to the 75uS pole. R155 (97k6) and C64 (33nF) looks like the 3180uS pole, while R154 (10k) and C64 (33nF) looks like the 318uS pole, combined and fed as NFB to the second differential amplifier as an active filter? Still trying to grasp the implementation, guess I'll have to read the seminal Lipschitz paper. \$\endgroup\$
    – Joe
    Nov 5, 2023 at 1:20

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