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Imagine a typical 2Oz/1Oz, 4 layer PCB with a stack-up, Sig/Pwr, GND, GND, Sig/Pwr. Your typical trace width/space would be 0.2mm/0.2mm, and a prepreg Dk of ~4, ignore the Core. Fastest signal on the board is highspeed USB.

These are the two stack-up up dimensions to consider.

Stack-Up A Stack-Up B
------SIG/PWR
===Prepreg [0.09mm]
-----GND
===Core
-----GND
===PrePreg[0.09mm]
-----SIG/PWR
------SIG/PWR
===Prepreg [0.2mm]
-----GND
===Core
-----GND
===PrePreg[0.2mm]
-----SIG/PWR

I understand that brining the GND layer closer to the SIG/PWR can help mitigate crosstalk by increasing the interplane capacitance. I also understand this interplane capacitance can also make hitting target impedances difficult, due to manufacturing constraints. Last I checked to hit 90Ohm diff impedance the trace width/space would need to be in the range of 0.15mm/0.2mm. These are two of the pros and cons I know about.

What are some other potential advantages and disadvantages to placing your GND plane close to you SIG/PWR layer; when compared to the standard 0.2mm SIG/PWR clearance.

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    \$\begingroup\$ hi! This is a bit of an open-ended question and requires a lot of system-level considerations. So, I guess a lecture on the topic would be more adequate than an answer could be: Rick Hartley lecturing on board layouts and stackups (frankly, he's also ranting about bad designs) . It's a bit lengthy, but chances are it offers a good intro and answers a lot of the "what are pros and cons"; if Rick Hartley's input left anything open, I bet that would allow for much more fine-grained questions! (I'd recommend watching the whole thing, anyways; \$\endgroup\$ Nov 5, 2023 at 0:10
  • \$\begingroup\$ on the way to the real-world stackup examples with up- and downsides, you learn why you should always keep sufficiently far away from RaspberryPi-designed ICs after seeing the literally zero-pins-assigned-to-ground pinout of the RP2040.) \$\endgroup\$ Nov 5, 2023 at 0:13
  • \$\begingroup\$ Thanks for the lecture recommendation. \$\endgroup\$
    – Lpaulson
    Nov 5, 2023 at 0:35
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    \$\begingroup\$ @MarcusMüller Sure the RP2040 has only one ground connection, but it's the whole underside of the package that is an exposed ground pad. Provides tight low-inductance ground connection directly to ground plane, far better than few tiny ground pads with wiring inductance. \$\endgroup\$
    – Justme
    Nov 5, 2023 at 0:51
  • \$\begingroup\$ @MarcusMüller, This question is intended of be open-ended, in engineering the answers is always "it depends" I get that - as much as I hate it. As you said, there are system level consideration, what are some of those considerations and how would the stack up dimension play a positive or negative roll? I want to hear about peoples experiences, the mistakes and successes that I haven't had the chance to make yet. \$\endgroup\$
    – Lpaulson
    Nov 5, 2023 at 0:52

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Without getting into considerable detail, the strongest effect is setting the dimensional scale of your transmission lines. That is, for microstrip of say 50-100Ω as is typical for onboard/digital signals, the trace width is some ratio to the height above substrate, typically 0.5-2, and the thinner substrate means thinner traces.

This is usually fine, as proto services typically offer finer trace width/space tolerances for finer laminates. This does limit you to modest copper thickness, as fine features are harder to make in heavier copper. (Typically up to 2oz is fine for 4/4 mils; check your fab's rules to be sure.)

The consequences for EMI are pretty small, as the height above substrate is still much much less than the distance from a nearby conductor (say, cabling above the board), or exterior (radiant) fields. Think in terms of the capacitive divider, from such a source, through air, to the trace, to GND.

But not to say it isn't different. The traces are also wider (for given impedance), so the facing area is larger too. It does increase. More that, either size isn't a problem for typical designs at commercial test levels. Long traces and pours are still an antenna concern, and this just changes the coupling factor a little bit (some dB).

Notice this says absolutely nothing about far more important EMC topics, such as signal quality, adequate grounding, avoiding ground slots, common-mode on cables or shields, etc. Board/layer thickness is mostly a manufacturing concern, and things like voltage withstand and trace resistance. There is of course the effect on transmission line losses at high frequency, but that's not much of a problem until ~Gbps at on-board distances.

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