0
\$\begingroup\$

If I have code like this:

logic [15:0] arr [0:3];
assign arr = {'d0, 'd1, 'd2, 'd3};

reg [1:0] k;
reg [63:0] out;

always @ (posedge clk) begin
    out <= {{16'd0}, {arr[k]}, 
            {arr[k+1]}, {arr[k+2]};
    k   <= k+2;
end

Is this valid syntax and will it synthesize into a multiported ROM?

\$\endgroup\$

1 Answer 1

1
\$\begingroup\$

It's valid syntax for SystemVerilog, but not synthesizable. I'm assuming k gets a value from some code you have not shown. Then you cannot assign it inside the always block as shown.

And you probably should define arr as a parameter, not as a variable

parameter logic [15:0] arr [0:3] = {'d0, 'd1, 'd2, 'd3};

It probably won't synthesize to a ROM. More likely a mux that gets optimized with constant inputs.

\$\endgroup\$
5
  • \$\begingroup\$ If I use the way you have shown it, is it synthesizable? I'm using k here as an index and it gets updated based on some conditions. And can I use out <= {arr[k+3]}; with the syntax that you specified? Is it synthesizable? \$\endgroup\$
    – lousycoder
    Commented Nov 6, 2023 at 19:25
  • 1
    \$\begingroup\$ You can only update k or any variable from one process to be synthesiable. Why are you assigning it to 0? \$\endgroup\$
    – dave_59
    Commented Nov 6, 2023 at 20:12
  • \$\begingroup\$ Have updated the code in the question \$\endgroup\$
    – lousycoder
    Commented Nov 6, 2023 at 20:59
  • \$\begingroup\$ would you like to recommend any books for sv synthesis? Have you authored a book on this topic? \$\endgroup\$
    – lousycoder
    Commented Nov 7, 2023 at 1:37
  • 1
    \$\begingroup\$ @lousycoder, your synthesis tool should have documentation for the synthesis rules. \$\endgroup\$
    – dave_59
    Commented Nov 7, 2023 at 8:08

Your Answer

By clicking “Post Your Answer”, you agree to our terms of service and acknowledge you have read our privacy policy.

Not the answer you're looking for? Browse other questions tagged or ask your own question.