ECP5: Determining max current an FPGA pin can sink from datasheet

Question

I have a circuit where I want to drive the CS# input on a SPI flash chip from an output pad on an FPGA. The flash IC's datasheet recommends putting an external pull up resistor to VCC on CS# to ensure that during power up the voltage at CS# will ramp at the same rate as the chip's VCC. Based on the flash IC's DC Electrical Characteristics table, I calculated that I could use as high as 1.5 MΩ pull-up in a configuration like this:

However, since 1.5 MΩ is a rather high upper limit on the pull-up resistor, I decided to look up the FPGA's maximum current sinking ability per I/O pad and per bank to see whether I could use a more normal-sized pull-up like 10k or 45k without damaging the FPGA.

That's where I ran into problems, and why I'm posing here to ask for help.

The FPGA is a Lattice ECP5U and it's main datasheet, table 3.7 in section 3.9 (page 50), appears to suggest that the maximum current an I/O pad can sink is 150 µA.

150 µA sounded surprisingly low to me, so I also consulted this FPGA's I/O pad configuration (sub-)datasheet. Tables 4.3 and 5.2 seem to state that single-ended LVCMOS33 I/O's can be programmed to source or sink up to 16mA.

The only sense I can make out of all this is that the FPGA's pad can sink up to 16mA if and only if it's configured as an OPENDRAIN=ON output (see sections 4.11.4, 5.2 and 5.3 of the I/O pad datasheet linked above, page 19).

But does this interpretation actually make sense? I'm not an FPGA expert, but normally open drain is used in multi-device, bidirectional buses like I2C. I've never seen open drain used to control a unidirectional, active-low chip select input. Is this typical for lower-end / budget FPGAs?

If anyone can see something that I'm misinterpreting or misunderstanding, I'd be grateful. Absent that, I would ask if there any downsides to using an open-drain output to drive an active-low chip select.

Answer 1

You are looking from wrong part of the datasheet.

The part you are taking 150uA from is from a FPGA pin which has an internal pull resistor turned on. These are input currents, not output currents.

You need to look at the Iol and Ioh section.

Any digital IO should be able to handle a reasonable pull-up like 10k or 4k7.

The FPGA has multiple IO pin strength settings from 4 to 16 mA. It is of course advisable to stay much below 4mA for a simple pull-up.

Answer 2

The table you added shows the current of the weak pull-up and pull-down resistors on each pin, if you select to use them. The current the output drivers can provide depend on the output standard you select. E.g. if you configure outputs as LVDS, then their drive current is 3.5 mA. If you chose LVCMOS or LVTTL outputs, you can configure the drive strength and select one of the values given in table 4.3 - the available values depend on the output voltage and the FPGA grade you're using.

Depending on the pin you chose, there will be a pull-up resistor active before the configuration is loaded - as your table states it will provide up to 150 µA, corresponding to something roughly equivalent of a 30 kΩ resistor.