I have previously posted I2C(Is pull up resistor mandatory for I2C?). But now I use an internal pull-up resistor from FPGA as @nanofarad suggested. I am using a Zedboard (FPGA) as the controller while the touch screen (FT5316) (https://files.waveshare.com/upload/0/08/Application-Note-for-CTPM.pdf) (https://files.waveshare.com/upload/9/9c/FT5x06.pdf) as the peripheral.

Now this time I use SCL as inout signal in VHDL in order to avoid clock stretching. And I use an internal pull-up resistor for SCL from FPGA. As for SDA, I use an external pull-up resistor.

Why does SCL not oscillate?

enter image description here

enter image description here

Update. the notation of the first picture is wrong. Here is the correct version.

Folks don't understand what I am doing here because I only posted a snippet of the waveform. The following is data I send to the slave.

b"0111_0000", -- 38 slave address (write)
b"0000_0000", -- 00 register address
b"1000_1010", -- 8A data
b"0000_0101", -- 05 data
b"0111_0001", -- 38 slave address (read)
b"1010_1011", -- AB register address
b"0111_0001", -- 38 slave address (read)
b"0000_0000", -- 00 register address

enter image description here

Update for Clock Stretching.

The following is a Modelsim simulation of clock stretching (SCL). enter image description here

  • \$\begingroup\$ What are the two screenshots? \$\endgroup\$ Commented Nov 8, 2023 at 15:00
  • \$\begingroup\$ @TimWilliams I just want people to know SCL is not working as expected from picture I posted. \$\endgroup\$
    – kile
    Commented Nov 8, 2023 at 15:02
  • \$\begingroup\$ It's pretty clear in the second picture that the slave did not ACK the first transfer, so naturally, the I2C controller aborted the transaction. \$\endgroup\$
    – Dave Tweed
    Commented Nov 8, 2023 at 16:21
  • \$\begingroup\$ @DaveTweed Yes, why did the slave not ack? What should I do? \$\endgroup\$
    – kile
    Commented Nov 8, 2023 at 16:26
  • 1
    \$\begingroup\$ SCL is going to stay high unless you drive it low. The process behind avoiding clock stretching is: (1) you drive the bus low for the low period and (2) you let it float high. If the chip needs to stretch the clock, it will force the bus to stay low. If the bus goes back to high, the chip is ready and you can then proceed with the next clock cycle when you're ready - you, as the initiator, will drive it low again. Or, if you know this device doesn't need clock stretching, you can simply drive it at a fixed rate. I'm not sure about the ACKs themselves, will need to look later. \$\endgroup\$
    – nanofarad
    Commented Nov 8, 2023 at 16:46

1 Answer 1


The buses are still push-pull on FPGA.

It can be seen from the spikes on the rising edges.

The slave chip tries to send an ACK and pull bus low, but the FPGA prevents it by pushing bus high. That is evident from the small dips in the bus high state, as both chips drive the bus to different states and FPGA is way stronger than your slave chip.

Also, pull-ups are usually external, because you can select how strong it is based on your needs. Using internal pull-ups may not work, as they are generally weak and allow only slower bus clock than what would be possible with external pull-ups.

As for the actual question why does not the SCL oscillate, it doesn't oscillate by itself, it's the job of the FPGA as master to clock data out of slave. You can refer to I2C standard or application notes for that.

  • \$\begingroup\$ Could you please point out those dips in the picture? I don't understand what dips you mean \$\endgroup\$
    – kile
    Commented Nov 8, 2023 at 17:04
  • \$\begingroup\$ @kile The points where SDA is 3.0V instead of 3.3V. \$\endgroup\$
    – Justme
    Commented Nov 8, 2023 at 17:06
  • \$\begingroup\$ It's not the job of FPGA as master when it's reading. It's the job of the slave when it's reading \$\endgroup\$
    – kile
    Commented Nov 8, 2023 at 17:18
  • \$\begingroup\$ @kile I already said it isn't the job of slave but master, and that's why your design does not work. I did not even imagine you thought it is the job of the slave. Most slaves don't even have clock outputs so how could they. \$\endgroup\$
    – Justme
    Commented Nov 8, 2023 at 17:22
  • 1
    \$\begingroup\$ Well, one of the features of I2C is "clock stretching", so it's actually a collaboration between initiator and responder. (That's why the initiator shall use open-drain with a weak pull-up, not push-pull driver) Many responder devices never drive (stretch) the clock, allowing the initiator to control it fully. Perhaps more fundamental though is that there is no change in direction on CLK between read and write as there is for SDA. \$\endgroup\$
    – Ben Voigt
    Commented Nov 8, 2023 at 17:26

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