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I see many people with some knowledge of PCB design, says it is bad practice to run high-speed signals of a "disconnected" ground place adjacent to the signal.

But no one shows practically what actually happens to the signal as it's traveling across this disconnected ground plane. If no one can show it, then it must be just nonsense, right...?

I understand that for high-speed signals the return path is directly under the signal trace.

I made a little sketch to show visually what I am on about: enter image description here

Can someone please show me what timestamps, t=3, t=4, and t=5 will look like?

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    \$\begingroup\$ Might help to look at this from another point of view: in theory (according to Poyinting's theorem), the energy flow of a circuit is between the forward and return path. That means, the energy flows between the signal line and the ground plane - essentially through the PCB substrate. If you introduce a discontinuity, that EM energy will leak into whatever part between the signal line and whatever different path it must take through the ground plane, causing interference and integrity loss. \$\endgroup\$
    – DELTA12
    Nov 8, 2023 at 21:46
  • \$\begingroup\$ Try search YouTube for Rick Hartley! Really good stuff. Link to an example \$\endgroup\$ Nov 9, 2023 at 16:57

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The scenario can be easily analyzed by extending the structures to infinity.

enter image description here

Suppose the quarter-planes extend forever to the left, right and bottom, and the trace stretches forever left to right. Or instead of quarters, we might say a lower half-plane with a vertical slot in it.

What does this look like?

On the left and right, we have a microstrip transmission line.

When the cross-section between a pair of conductors is consistent, we have a transmission line. It might not be a very good or useful one, for random general cross-sections, but that's not important to the fields; a transmission line it will be.

In this case, the cross-section is very simple: a flat trace over a partial plane.

enter image description here

(Notice the scallop on the right side, suggesting the plane continues and this is a partial section.) There is some trace width \$w\$, a height \$h\$ above the plane, and the distance \$d\$ from the edge of the plane (not shown) is significantly more than \$h\$ and \$w\$ so that we can ignore the edge.

The thickness of the trace is also a parameter, and the dielectric between them (since PCBs aren't conductors floating in air, but bonded around fiberglass or whatever). The thickness of the plane isn't material however (not at high frequencies).

I won't add formulas here, because for one they're all approximations (an exact solution for microstrip is lengthy, if possible (in closed form) at all?), and anyway it's not material here. What's important is that the impedance is defined by the ratio of dimensions.

What is transmission line impedance? Suppose we have a wave coming in from the left. The instantaneous ratio of voltage, between a point on the trace and the corresponding point on the plane below it, has the ratio \$Z_o\$ to the current flowing on the trace at that point. Thus, the ratio of voltage to current depends on the aspect ratio of the transmission line.

It is another fundamental property of transmission lines, that waves are always, and only, propagating up or down the line at the (local) speed of light. Proof requires Telegrapher's Equations or EM field theory, and again isn't important here; we can take this for granted for now. (Further reading is suggested; these are relevant keywords to search on.)

It's also linear and reversible, so without loss of generality, we can consider a wave in one direction, and aren't missing out on any behavior otherwise.

Consider the wave, then:

enter image description here

The dashed lines imply the position of the trace over the planes, in an isometric view.

Suppose a wave enters the picture from the bottom left, on trace T, current shown with the red arrow. This has some voltage above the plane P1, and induces an image current in P1 shown below.

An instant later, the wavefront reaches the slot, the ground current cannot continue, and instead spreads out crosswise along the edge of the slot (the split arrow). The current in the trace is continuous (approximately the same current is flowing above the left/right edges of the slot), therefore a "new" image current is induced in plane P2 (the split arrows). Both currents around the slot, spread out equal and opposite.

An instant after the wavefront crosses the slot, a diminished amplitude continues onward to the top-right, with image currents in the plane flowing beneath it. Some of the wave energy from the trace has coupled into the slot mode, and therefore the wave is attenuated along its length, while energy flows off in different directions -- along the slot itself (the bottom-right and top-left arrows).

One final change occurs when the current flowing along the slot, reaches the open edge (after electrical length \$d\$). This current flows out along the infinite edges of the quarter-planes, eventually radiating into space -- notice the geometry is identical to a dipole, or a topological dual thereof.

Topology is very important to electromagnetism. We can identify analogous cases with seemingly very different setups, yet the same dynamics, and the same rations governing their properties (like velocity and impedance). Case in point here: the slotline.

A gap between two infinite half-planes gives the slotline structure. We can understand this shape by considering a differential ribbon pair (two traces side by side, no ground plane beneath or around), then letting their width increase to infinity, while keeping their gap constant. In the narrow case (w ~ d), the trace pair looks like a parallel-wire transmission line; the fields distort in shape as we extend the far edges, but the impedance and velocity change surprisingly little, and we have transformed the structure into the infinite slotline.

Thus, slotline can be treated as a parallel-pair transmission line. Altogether, we have this equivalent circuit:

enter image description here

Notice SPICE TLs can be grounded arbitrarily at either end; their connections are ideal ports, i.e. current only flows between VI and GND, or VT and VS, of LLTR2; no current flows along the length, between VI and VT, or GND and VS. This idealizes a real transmission line, where the common mode impedance can be made very high (kΩ) with the use of magnetic cores, or isolation transformers. (Indeed, transmission lines are a generalization of transformers, but I won't get into that here; another breadcrumb to follow if you like.)

This mirrors the physical situation, that there ultimately is no absolute voltage reference to take as ground, and we must always carefully define our voltage-measuring path because in general the measurement is path-dependent[1].

I have assigned somewhat arbitrary impedances and times (electrical lengths) to the TL elements. Read "100ns" or "200ns" as "very long" or infinite; of course we have to pick some point at which to begin the simulation, so LLTR2 can't be infinite. The \$d\$ length is a bit exaggerated at 30ns (though if you wanted to set up a demo like this, say with lots of aluminum foil, you could lay out a good 9m or so this way). The impedances will be roughly typical for real PCB geometry.

Note that R2, R3 and R4 terminate their lines perfectly, meaning no reflection comes back, and indeed the length of these lines is a free variable -- they could be any length (except LLTR2 for initial delay purposes as mentioned), including zero, and the same terminal impedance (at VS or VT and GND) would be seen. I opted to show them, to make the model more visually explicit.

R1 does not match, a nod to the line edge approximating a dipole antenna structure, projecting into the impedance of free space, or half of it rather. This value might actually be quite a bit lower (normally a wire dipole is 50-70Ω, albeit at resonance, and this infinite dipole can't resonate), but anyway it's just to show a mismatch somewhere, and the bump every 30ns is evident.

enter image description here

I also didn't show V1 parameters but it's obvious enough from the waveform; VI steps up by half or 2.5V, so the VPULSE is a 0 to 5V step, 1ns edge, 10ns delay, and stays high for longer than the simulation time.

A whole lot of nothing happens for the first 100ns as LLTR2 is charged up; then the wave front reaches the middle nodes. There, VS jumps down as VT jumps up; roughly in equal and opposite amounts, because the parallel combination LLTR1 || LLTR4 is 60Ω, and we have the Thevenin equivalent of LLTR2 (70Ω) feeding the series combination of LLTR1 || LLTR4 (60Ω) plus LLTR3 (70Ω). Note that the equivalent does not sum to 70Ω, so some wave is reflected back up LLTR2, evincing the step in VI at 210ns (which is termianted in R2, so we needn't follow that event further).

These waveforms are easily calculated, by the way, following a bounce diagram.


As for what happens in practice? Who knows. The problem is very weakly defined, almost certainly not representing a practical situation. Which does at least make it easy to analyze,

Are there any applications to this structure? Well, if we want to tap RF power from a signal trace -- perhaps to connect the slotline to an antenna structure, and perhaps chain some of those together to make a phased array -- this mechanism can be used to couple them (the slot and trace), without having to build a transformer, or LC (lumped equivalent) matching network, and the coupling is simply the ratio of impedances at the crossover point. Change the ratios appropriately, as power decays along the string, and you can end up with N antennas at 1/N power each; or whatever ratios happen to be desired for the array.

Note that the final antenna in such a chain would be terminated into a line of 0Ω, i.e., a short circuit. We can also use this structure as an adapter or mode converter, from the microstrip or stripline mode of the trace, to the slotline mode of the slot. Simply tie the trace to the far edge of the slot with a via, and now the trace and slot are joined directly. If their impedances match, then it's practically seamless to the wave. (In practice, there will always be some length (height) of the via, and it won't sit perfectly on the edge but has some pullback due to minimum annular ring. But that only matters at the 10s of ps scale.)

Since we are simply coupling transmission lines of different types, we can also readily understand what happens when the slot isn't infinite. Simply cut that TL shorter, and add the respective impedance in place. This gives us the case for a finite-length slot: simply use a TL of the given length, and short the far end of it. For the both-ends-closed case, do the same for both LLTR1 and 4. Notice this gives a slot antenna, the dual of the dipole; therefore it is also an effective radiator. (Slotline itself isn't exactly ideal transmission line geometry; notice I've left off about radiation so far, except in reference to the slot's open end, which was the more interesting aspect before, so worth covering at the time.)

Or perhaps the slot isn't a slot in a thin plane, but suppose the planes are infinite cuboids and so the slot has infinite height. Again we're only interested in the surfaces of these cuboids (skin effect), so we only need to consider a thin foil, as long as it's contiguous. Now waves crossing the slot are directed into a 2D parallel-plate transmission line; they spread out with distance, impedance dropping (wavefront width increasing) as they go, so this isn't very interesting for propagation purposes, but it does give us an important insight: the edge of this infinite parallel plane has a transient impedance Z ~ 1/t. Impedance decreasing with time is the definition of inductance, so we will measure inductance here. We will also measure a coupling factor between traces crossing nearby, where the coupling factor is reciprocal with distance.

Continuing with the infinite-cuboid-slot idea, recall that only the surfaces matter at high frequency. We can take that infinite parallel plane structure, and bend it around in space: the fields between it don't care how it's bent, at least if the curvature is mostly larger than the distance between planes. Well, with a minor compromise due to local curvature at just one point, suppose we bent the parallel-plate structure over all the way so it is parallel with the top planes. Now we have a stack of three planes on say the left side, and just one on the right. The right plane is a continuous sheet, planar on the right, but jogging underneath the left plane. Suppose we approximated this in a PCB by plating the top layer, then via-stitching it to the bottom layer, and extending the bottom leftwards. The top and middle layers can be welded into a single sheet of metal: as long as the sheet is thicker than several skin depths, this occurs without loss of generality. (Which will be the case for average PCB material above 10s of MHz.) Thus we have a parallel-plate pair on the left, and a single plane on the right. With a trace running atop both of them (okay, maybe this should be a 4-layer board, and the planes are inner layers, and the bottom signal layer is unused).

Well, in the above case, we would simply have the situation where a signal travels over one plane, that plane ends, and another, initially underneath the first plane, rises up to meet the signal. The image current of the signal extends down into the gap between planes. It spreads out as it propagates along the 2D transmission line structure, eventually diluting into the average fields between those planes (which in practice, will be terminated by bypass capacitors scattered about the planes). Aha, we have derived the case for a microstrip trace crossing between power planes, on top of a ground plane. And now we can immediately see the value in via stitching or bypassing between planes, where signals cross over gaps between them.

Or why differential traces are preferred: for high-speed differential signals, signal energy delivers equal and opposite image currents into the plane gap, which cancels out a modest distance (several pair-separation distances) within the plane; the differential current remains more-or-less confined, preserving signal quality. Likewise, any offset voltage between the planes, results in a common-mode error induced on the pair; but if the electrical delays along each trace, from any given gap or other source of disturbance, to the receiver, are equal, then the noise remains balanced -- common -- and a fully differential receiver subtracts it out, no problem whatsoever. (At least as long as it remains differential, of course; the input common mode range must not be exceeded. This requires little design effort to achieve; hence the broad success of high speed differential standards.)

What about signal quality in all of this?

Well, as can be seen from the simulation, if the gap has considerable impedance, so too the impact on the signal (VT) will be large. The impedance can be minimized by using a "thick" slot -- instead of a complete air gap between two planes, if they overlap for some distance (or are both backed by a common ground, say), that distance factors in to the "thickness" of the slot -- and so we can maintain good signal quality when passing signals between power domains on a large PCB. But we can see we are introducing supply noise in the process (some of the signal couples into both supply planes), and we can easily avoid both by at least terminating the planes where the crossing occurs (add local bypass caps), or preferably routing the signal over contiguous ground instead.

We can also see, if the gap is oddly shaped, if it's open or shorted nearby, if other traces route over the same gap, whatever -- we'll get odd reflections induced back on the signal trace, in both directions (transmission and reflection).

Signal quality is usually the secondary concern, because of a couple reasons: EMI levels are just close enough that, if handled poorly, regular digital logic signals will easily violate them; and, with binary signaling being most common, the noise margins are an adequate fraction of the full swing (i.e. for CMOS, typically 20 or 30% of VDD), so as long as signal bounce/settling is within this margin immediately following an edge, we don't care too much.

Conversely, this gives us the situations where signal quality is the primary concern. Perhaps EMI is solved by shielding (use stripline instead of microstrip traces; use shields over the PCB; use a metal enclosure; etc.), perhaps signal quality just need to be extremely precise (say for extremely low jitter timing applications, or precision analog RF applications). And based on slot impedances and such, we can calculate whether a given crossing is acceptable in the application, and whether to avoid it.

[1] Say we didn't measure voltage directly along the \$h\$ vector, but with a dogleg path that runs parallel to the trace for some distance along the way (that is, a sort of directional coupler structure): then we would get the sum of the trace's voltage over ground, plus some coupling due to current flow within it. Which need not match, in general, because in general there are two waves, incident and reflected, and we can't separate the two directions with just a point measurement!

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They do say but you probably don't grasp enough to recognize it when you see it. The reason I say this is your question is also not framed appropriately for what you want to know. Your diagram of just a small segment part of the PCB is insufficient. All paths, both DC and AC coupled, are fair game for the signal. It is also a transmission line issue spatially spread across the board, not the state of the signal state at one point. These reasons mean you would need the entire PCB to begin to trace out how the signal propagates across the board over time. In addition, the digital states in your diagram are also insufficient because it is not a digital issue. It is an analog one (being the transmission line that it is).

The answer you are asking for would not come in the form of digital logic states at a single point at various time stamps, but a progression of analog voltages over time at multiple points across the board along the signal loop. Multiple simultaneous voltage graphs, if you will, each one representing the voltage at a different point along the signal loop.

Or, if the graphs were animated, it could plot the instantaneous voltage for multiple points simultaneously at the same point in time on the a single graph, and then represent the progression through time with an animation. Then you have to look back and forth at a location on the graph to see where it actually is on the PCB. That would kind of look like this if it the graph's axis was mapped to the signal path on the PCB layout rather than a schematic.

https://helloworld922.blogspot.com/2013/04/online-transmission-line-simulation.html

(Go to the link, it's animated which won't show on here)

enter image description here enter image description here

I understand that for high-speed signals the return path is directly under the signal trace.

The return path is not directly under the signal trace. You want this to be the return path since results in the smallest loop area and the path of least inductance. But if you provide no copper to do this, then the path does not exist and cannot be taken.

What the signal always does is take the path of lowest impedance path. If you have a gap lower frequency components such as those near DC will find a detour around the gap; Somewhere on the other side if the PCB if necessary. Higher frequencies components will capacitively couple across gaps if this results in a lower impedance. All these result in a larger loop area which results in higher inductance and more noise.

But did you notice in the previous paragraph how I implied that different frequency components in a signal can take different paths around the PCB? That means that technically the two forms of answers I gave about were not quite accurate since they both assume a single looping path on the PCB for the entire signal. A full answer would kind of look like an animation of the entire circuit board under a progression of graduated colours representing different voltages. This would account for how the frequency components in the same signal can spread out and take different paths, especially if (undesirable) capacitive coupling is involved.

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  • \$\begingroup\$ Because an i2c communication is not a complementary pair signal, and is also terminated, is an i2c communication modeled by the simulation you have presented? \$\endgroup\$ Nov 9, 2023 at 11:33
  • \$\begingroup\$ @MicroservicesOnDDD Corrected. Thanks. I don't see why it wouldn't be modeled by said simulation. \$\endgroup\$
    – DKNguyen
    Nov 9, 2023 at 15:45
  • \$\begingroup\$ I like the lumped constant transmission linedepiction. The OPs question can be reframed by saying one or two of the ground points in the middle are removed leaving an inductor in series with two transmission line segments. \$\endgroup\$
    – KalleMP
    Nov 9, 2023 at 21:39
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The signal itself will not see much, if any effect, unless the gap between return planes is enormous - a fraction of the equivalent length of the edge of the signal. The gap causes a capacitance change in the signal trace, and how much this affects signal depends on the amount of capacitance change and the edge speed of the signal.

What a gap does do is to increase the inductance of the trace + return path by increasing the area of the current loop. In some cases, this loop can act as a loop antenna, radiating emissions that can cause EMC problems.

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The exact waveforms won't be predictable without a lot of details. You may see undershoot, overshoot, non-monotonic rise/fall patterns, radiated emissions, and/or excessive interference with other devices.

The reason is that a high or even medium frequency signal will induce its own return current in the plane. Remember current always has to make a round trip in lumped systems, so it's coming back one way or another, and the smaller the loop between the signal and return currents, the better for signal integrity as well as EMC.

This is all fine and well if the ground plane is contiguous, but if you run over a slot in the ground plane, the return current has to make a detour of some length. Now, you've gone from having a transmission line to having a loop antenna. Further, the return path is now physically longer than the signal path, so the return current will be out of phase on the other side of the gap, leading to signal integrity issues. Also remember antennas are symmetrical, so it's a good practice even with low frequency analog lines that might be susceptible to external interference.

There's a lot more to consider, such as running a signal from one side of the board to another (which is near a different plane), stitching caps, and optimal via placement. Keith Armstrong had a good tutorial online a few years ago, but I can't find it now. There's numerous books and videos on the subject too, just google "slotted ground plane emc."

https://www.youtube.com/watch?v=CiZ5VAnF8SY

https://incompliancemag.com/article/slots-in-gnd-planes/

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What you are asking is a special case which is a product of many things. The exact answer how it will look like needs a simulation program with input parameters such as geometry of the PCB wiring, planes, slots, PCB stackup, material for dielectric constant, thickness between ground plane and signal wire, rise time and duration of pulse edge. A field solving program like this could cost more than a small car.

In general, you just have an impedance discontinuity for some length and time of signal flight time, and no route back for the return current. For a pulse with fast edge any discontinuity will surely affect the edge, so you can be sure it is not nonsense even if nobody has not shown you the exact situation you want to know.

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