I've 10 4 MHZ crystal oscillators. I need a 16MHZ clock signal. Can I connect multiple 4MHZ oscillators somehow (serial, parallel) to get 16MHZ?
No, connecting them in series or parallel won't get you a higher frequency.
What you're looking for is a Phase Locked Loop or PLL. Here's a block diagram:
A Voltage Controlled Oscillator (VCO) generates the output frequency. This signal is divided and then compared to the input frequency in the Phase Detector. If the two frequencies aren't the same, the output frequency is adjusted. This is called a feedback loop: you feed the output frequency back to adjust it.
The Pre Divider allows you to multiply the input frequency with a floating point number. For example, when you want to multiply by 2.5=5/2, you first divide the input frequency by 2 and then multiply by 5.
There are ICs available that have a PLL implemented, like the LM565. On page 10 of the datasheet a typical application circuit for a ×10 multiplier is given:
By changing the voltage divider (the external IC) you can make it a ×4 multiplier.
Implementing a PLL will cost some effort and space - consider buying a new crystal.
Connecting crystal oscillators in series or parallel won't get you a higher frequency.
Since 16 MHz is a common crystal frequency, 16 MHz crystals are relatively low cost, so it's probably simplest in this case to buy a new 16 MHz crystal.
There are cases where it's not possible to get a crystal of the desired frequency -- sometimes the exact frequency you want is not a "common" frequency and so crystals at that exact frequency are expensive and long lead-time "custom frequency crystals"; or perhaps you want a frequency above 50 MHz -- fundamental crystals are difficult or impossible to make at such high frequencies.
To get a desired frequency when you can't get a fundamental crystal at that frequency, there are 7 popular approaches:
- Drive some "common" crystal in one of its overtone modes, which occur near odd multiples of its fundamental resonant frequency. Such an "overtone" oscillator circuit includes LC filter to select only the desired overtone.
- Drive a "common" crystal in the normal fundamental oscillator circuit. Then connect the oscillator output to the input of a frequency multiplier. (A full-wave rectifier is sometimes used to make a frequency doubler).
- Build some oscillator without a crystal and try to manually tune it to run at the desired frequency.
- Build some oscillator without a crystal, and use a fractional-N synthesizer (a kind of phase-locked loop PLL) to automatically tune it to a frequency at some ratio N/M times the frequency of a separate crystal in a normal fundamental oscillator circuit.
- Build some oscillator without a crystal, and use a integer-N synthesizer (a kind of phase-locked loop PLL) to automatically tune it to a frequency at some integer multiple N times the frequency of a separate crystal in a normal fundamental oscillator circuit.
- Drive a "common" crystal in the normal fundamental oscillator circuit. Then use some sort of frequency divider to generate a frequency at some 1/N times the crystal frequency.
- Drive a "common" crystal in the normal fundamental oscillator circuit. Then use some sort of http://en.wikipedia.org/wiki/dual-modulus_prescaler to generate a frequency at some ratio N/M times the crystal frequency.
One approach which can work reasonably well in some contexts for doubling a clean square wave clock signal is to XOR the clock signal with a slightly-delayed version of itself. If, for example, one starts with a square wave signal which is 120us high and 130us low (nominally square, but actually a little off), and uses a delay of 50us, one would end up with a wave which, during every 250us interval, would be high for 50us, low for 70, high for 50, low for 80. Not exactly a clean 8MHz signal, but good enough for many purposes. If all clocking occurs on the rising clock edge (as is pretty common), the length of the delay won't matter, provided that it's at least equal to the minimum required high time, and provided that when added to the minimum required low time the result does not exceed the shortest high or low time in the original signal.
The aforementioned approach is pretty good for doubling the frequency of a clean and symmetrical square-wave clock signal. Such a signal, it will output a clean but somewhat non-symmetrical output. Attempting to put the output of such a circuit through another will generally yield output which is likely to have a significant "putt putt [pause] putt putt [pause]" aspect.
If one wants to do something more than double a frequency, it may be possible to use multiple delays along with a multi-input XOR gate or cascaded sequence thereof, such that each edge on the input signal will generate a rapid sequence of pulses. For example, if one were starting with a 4MHz wave and wanted 32Mhz, one could arrange to have each nominally-125ns edge on the original signal generate a sequence of four pulses each 30ns on and 30ns off. The output wouldn't be very smooth or uniform, but there would be precisely eight pulses in each 250ns interval.
Such "putt-putt-wait" circuits produce output which isn't nearly as clean as that of a PLL, but they have a significant advantage: when a PLL is started, it may take hundreds of microseconds to stabilize before its output is usable. By contrast, the output of a putt putt wait circuit may be usable within a microsecond of when it's started. Consequently, such circuits may be very useful in cases where it's necessary to perform a quick sequence of operations each time an input changes and there is no other running clock. If one uses a PLL which is frequently started, run very briefly, and stopped, one might waste more energy waiting for it to stabilize on each startup, than would be spent actually running before the PLL shuts down again. A putt-putt-wait system by contrast could be reasonably efficient even if it ran for less than a dozen cycles after each wake-up.