I am trying to simulate NMOS and PMOS power transistors in LTspice, but I keep getting error messages about the NMOS being duplicate.
Some of the earlier LTspice file is here. I am trying to have a 5V drain supply across a resistor and driving it with a sine wave on the gate 5V bias and amplitude 5V to see the resistor voltage go "on" 5V and "off" 0V, still without getting the simulator to start to succeed. I am lost with the LTspice documentation and movie still.
Version 4
SHEET 1 968 680
WIRE 432 0 32 0
WIRE 336 64 208 64
WIRE 432 96 432 80
WIRE 32 112 32 0
WIRE 208 112 208 64
WIRE 336 176 336 64
WIRE 384 176 336 176
WIRE 32 224 32 192
WIRE 208 224 208 192
WIRE 432 224 432 192
FLAG 32 224 0
FLAG 208 224 0
FLAG 432 224 0
SYMBOL voltage 32 96 R0
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR InstName V1
SYMATTR Value 5
SYMBOL voltage 208 96 R0
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR InstName V2
SYMATTR Value SINE(5 5 100)
SYMBOL res 416 -16 R0
SYMATTR InstName R1
SYMATTR Value 1
SYMBOL nmos 384 96 R0
SYMATTR InstName M1
SYMATTR Value ""
SYMATTR SpiceModel .model MyMOSFET NMOS(KP=.001)
TEXT -2 248 Left 2 !.tran .01
Update:
I am using LTSpice XVII ; I tried copying the source code from G36 into the the .asc file but it did not work. However, it was a good enough a hint to make substantial progress, together with the link provided in that answer of: Stack Exchange Electrical Engineering: Simulating Power PMOS using LTSpice. I updated the PMOSbasictest4.asc file using a text editor, outside of LTSpice XVII and then I imported it again, updating everything according to the linked example (picture is important).
The copy of the PMOSbasictest4.asc code is here:
Version 4
SHEET 1 1128 680
WIRE 112 48 -16 48
WIRE 352 48 112 48
WIRE 352 64 352 48
WIRE 304 80 240 80
WIRE 112 160 112 128
WIRE 240 160 240 80
WIRE 240 160 112 160
WIRE 352 176 352 160
WIRE -16 192 -16 48
WIRE -16 288 -16 272
WIRE 352 288 352 256
FLAG -16 288 0
FLAG 352 288 0
SYMBOL res 336 160 R0
SYMATTR InstName R1
SYMATTR Value 1
SYMBOL voltage -16 176 R0
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR InstName V1
SYMATTR Value 12
SYMBOL voltage 112 32 R0
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR InstName V2
SYMATTR Value 4.8
SYMBOL pmos 304 160 M180
SYMATTR InstName M1
SYMATTR Value MyPMOSFET
TEXT -48 312 Left 2 !.tran .01
TEXT 464 168 Left 2 !.MODEL MyPMOSFET PMOS (LEVEL=2 KP=1.4 VTO=-3.11)
But the question is still not completely answered in terms of what I need.
I want to simulate the Vishay IRF9510 power P-channel MOSFET: https://www.vishay.com/docs/91072/91072.pdf
To make the answer complete, I still need the actual needed parameters.
Right now I have some modulation simulated, but with a different transistor model:
I have also made some progress in getting modulation to work with the example P-channel MOSFET parameters. (Thank you for the answers that provided inspiration of how to get here! I am almost finished!)
Version 4
SHEET 1 1128 680
WIRE 112 48 -16 48
WIRE 352 48 112 48
WIRE 352 64 352 48
WIRE 304 80 240 80
WIRE -368 112 -432 112
WIRE -288 112 -368 112
WIRE -368 144 -368 112
WIRE -288 160 -288 112
WIRE 112 160 112 128
WIRE 240 160 240 80
WIRE 240 160 112 160
WIRE 448 160 352 160
WIRE 352 176 352 160
WIRE -16 192 -16 48
WIRE 448 208 448 160
WIRE 480 208 448 208
WIRE -368 240 -368 224
WIRE -288 240 -368 240
WIRE 240 240 240 160
WIRE -368 256 -368 240
WIRE -16 288 -16 272
WIRE 352 288 352 256
FLAG -16 288 0
FLAG 352 288 0
FLAG -368 256 0
FLAG -432 112 V10-711
IOPIN -432 112 Out
FLAG 240 240 VMODDrain
IOPIN 240 240 In
FLAG 480 208 VR1
IOPIN 480 208 Out
SYMBOL res 336 160 R0
SYMATTR InstName R1
SYMATTR Value 1
SYMBOL voltage -16 176 R0
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR InstName V1
SYMATTR Value 12
SYMBOL voltage 112 32 R0
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR InstName V2
SYMATTR Value SINE(4.8 5 100)
SYMBOL pmos 304 160 M180
SYMATTR InstName M1
SYMATTR Value MyPMOSFET
SYMBOL res -304 144 R0
SYMATTR InstName R3
SYMATTR Value 10K
SYMBOL voltage -368 128 R0
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR InstName V3
SYMATTR Value 10.72
TEXT -48 312 Left 2 !.tran 0 .1 0 0.01
TEXT 424 128 Left 2 !.MODEL MyPMOSFET PMOS (LEVEL=2 KP=1.4 VTO=-3.11)
Question update:
I received an excellent LTSpice help link reference in the answer from @Ste Kulov in his comment, that matches the help pdf in the directory of the installation of LTSpice XVII.
I took the datasheet and its graph of the V-I curve at 5-Volt \$V_{SG}\$ (Source-Gate voltage is 5V). For a source-gate voltage of 0 Volt, the LT-Spice Level 1 Shichman-Hodges equations have that the \$I_{SD}\$ (from Source-to Drain current) is 0 Amps. Also, from the data-sheet, below the Source-Gate absolute threshold voltage, \$V_{sg}<|V_{th}|\$, the Source-Drain current is very small, essentially zero for the current design-purposes.
In addition, for the "turn-on" state of the PMOS MOSFET, I drive the voltages as follows:
$$V_{SG}=5.0 \text{ Volts }$$
So I only need to take data from one of the curves, the \$-5 \text{ Volt}\$ curve in particular, from the data-sheet. I can use GIMP software to take data-points from the curve as pixels, and make mathematical conversions later.
I started with the datasheet to get a couple of data-points (21 data points), from the \$25^\circ C\$ data-set:
I have a spreadsheet that I derived the model parameters from. I am hoping to update this further.
Still left for the answer: how to take those parameters and verify in LTSpice XVII is working fine. Also, how to set zero default capacitance values, as the frequency of operation is too low to make capacitance an issue. And of course a comparison of the Vishay model and the datasheet, especially the model parameters like \$V_{th}\$ that can vary between -2 V and -4 V.
Question Update:
Introduction to he Applicable Theory
From Shichman-Hodges equations for the P-channel MOSFET (which has \$V_{th} < 0\$ for the transistor under consideration):
"DC model selector. Level 1 is the Schichman-Hodges model."
$$\text{Cutoff Region, } 0 \le V_{SG} \le |V_{th}|$$
$$I_{DS}=0.0 \longrightarrow I_{SD}=0$$
For the "Cutoff Region", the current entering into the Source and exiting the Drain and it is modeled as zero Amps. From the IRF9510 Data Sheet, at \$V_{SG}=0\$ and \$V_{DS} > -100 V\$ then \$I_{SD} \lt 50 \mu A \$ which is negligible (essentially zero) for the purposes of this model. The LTSpice Help is available at this link, selecting "Dot Commands -> Model -> MOSFET". The equations themselves were taken from the previous link.
$$\text{Linear Region, } V_{SD} \le V_{SG} - |V_{th}|$$
$$I_{SD}= \text{ KP } \frac{W_{eff}}{L_{eff}} \left(1+\text{LAMBDA } V_{SD} \right)\left( V_{SG}- |V_{th}| – \frac{1}{2}V_{SD}\right) V_{SD}$$
$$\longrightarrow I_{SD}= \frac{\text{ KP }}{2} \frac{W_{eff}}{L_{eff}} \left(1+\text{LAMBDA } V_{SD} \right)\left( 2 \left(V_{SG}- |V_{th}| \right)– V_{SD}\right) V_{SD}$$
\$\text{LAMDA }\$ is positive for PMOS and NMOS transistors according to page 3 of this link.
$$\text{Saturation Region, } V_{SD} \ge V_{SG} - |V_{th}|$$
$$ I_{SD}= \frac{\text{KP }}{2} \frac{W_{eff}}{L_{eff}} \left(1+\text{LAMBDA } V_{SD} \right)\left( V_{SG}- |V_{th}|\right)^2 $$
$$\text{Saturation Voltage }V_{sat}, V_{\text{SD sat}}=V_{SG}-|V{th}|$$
At the saturation voltage \$V_{\text{SD Sat}} \$, the saturation region and linear region meet at one point. This can be revealed by substituting \$ V_{\text{SD sat}}=V_{SG}-|V{th}| \$ into both the equation for Linear Region and for the Saturated Region: $$ I_{SD}= \frac{\text{ KP }}{2} \frac{W_{eff}}{L_{eff}} \left(1+\text{LAMBDA } V_{SD} \right)\left( 2 \left(V_{SG}- |V_{th}| \right)– V_{SD}\right) V_{SD} $$ $$ =\frac{\text{ KP }}{2} \frac{W_{eff}}{L_{eff}} \left(1+\text{LAMBDA } V_{\text{SD sat }} \right)\left( 2 V_{\text{SD sat }}– V_{\text{SD sat }}\right) V_{\text{SD sat }} $$ $$ I_{\text{SD sat Linear Region}}=\frac{\text{ KP }}{2} \frac{W_{eff}}{L_{eff}} \left(1+\text{LAMBDA } V_{\text{SD sat }} \right)\left(V_{\text{SD sat }}\right)^2 $$ At the Saturation Region Point: $$ I_{\text{SD sat}}= \frac{\text{KP }}{2} \frac{W_{eff}}{L_{eff}} \left(1+\text{LAMBDA } V_{\text{SD sat}} \right)\left( V_{\text{SG sat}}- |V_{th}|\right)^2 $$ $$ I_{\text{SD sat Saturation Region}}=\frac{\text{ KP }}{2} \frac{W_{eff}}{L_{eff}} \left(1+\text{LAMBDA } V_{\text{SD sat }} \right)\left(V_{\text{SD sat }}\right)^2 $$
It is important to realize that for \$I_D \ge I_{\text{D Sat}}\$ that the equation for \$I_D\$ is that of a line. So statistical linear regression approaches can be used to find the parameters over the applicable region and then apply these to the full solution.
Introduction to he Applicable Data
The X-Axis and L-Axis Data Points
The applicable data points taken include \$0\text{ Volts}_{SD} \longrightarrow 0\text{ Amps}_{SD}\$, the other 20 x-axis data points, and the other y-axis data-points. A simple mathematical formula that determines \${Amps}_{SD}\$ and \${Volts}_{SD}\$ is then determined, evaluated, and its relative error is determined.
The Data Points From the SD V-I Curve for the MOSFET
After that, pixel sample data points are taken from the V-I curve of the device also using the GIMP Gnu Image Manipulation program in Ubuntu Linux. Then the corresponding voltage and current data values are determined from the data-sheet curve. It is to be appreciated that with real devices, sometimes an actual measurement deviates somewhat from what should be expected, sometimes from experimental error, and sometimes in the limitations of the expectations for the device under test (DUT).
