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The question is simple (and perhaps silly to many of you).

We all know that the conversion time of an ADC is the time it takes to perform a complete conversion.

But what is meant by "complete conversion"?
I guess it means converting the analog signal to a digital value, right?

So, let's assume that I have a conversion time (not sampling time, let's not get confused!) of 0.3 μs and I declare ADC_BUF_LEN = 1024 samples .. does that mean that the ADC will take 0.3 μs ×1024 = 307 μs to convert all these samples to digital values?
In other words that my buffer of 1024 elements will be filled after 307 μs.

This is probably a trivial and stupid question, but I really need to understand the basics of this topic.

Thanks!

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    \$\begingroup\$ You probably have several delays, pipeline in the AD conversion and if serial output, time to output each bit serially. Do you have figures for them? \$\endgroup\$
    – winny
    Commented Nov 10, 2023 at 17:03
  • \$\begingroup\$ @winny It might be interesting to find these delays; I am using the ADC from the STM32F407discovery. Maybe I'd better turn a GPIO on and off as soon as half a buffer is filled, though, so I can see directly through an oscilloscope how long it took to fill it ... without doing hand counts and looking up datasheets. \$\endgroup\$
    – KaleM
    Commented Nov 10, 2023 at 17:16
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    \$\begingroup\$ Please link to the source where you read these terms. Also, what is the relevance of the BUF_LEN = 1024 samples to an ADC? Did you have a specific ADC in mind that requires this parameter to be set up in the ADC internally or, is it something else? \$\endgroup\$
    – Andy aka
    Commented Nov 10, 2023 at 17:17
  • \$\begingroup\$ @Andyaka The numbers I used are just an example ... I edited the post where I specify it. Let's reason about my example without checking whether it is a real/existing scenario \$\endgroup\$
    – KaleM
    Commented Nov 10, 2023 at 17:20
  • \$\begingroup\$ I'm talking about the phrases "ADC conversion time" and "complete conversion" <-- I'm not talking about the actual times in microseconds. \$\endgroup\$
    – Andy aka
    Commented Nov 10, 2023 at 17:22

3 Answers 3

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You probably understand "sampling time": This is the interval during which the input voltage is affecting the internal value which will be converted. "Conversion time" comes after that; changes of input voltage are no longer influencing the result, but the digital result isn't determined yet.

After conversion of the first value is complete, the ADC isn't ready to start converting the second value, it needs to go through the sampling process.

If you are scanning multiple channels, there may be some switching time in the input mux and settling time, before sampling can begin.

The shortest time between consecutive samples (highest permitted sampling rate) will be the sum of the time needs for each of these phases of acquisition (channel switch, settle, sample, convert).

I don't completely agree with Scott's definition that "the digital value is guaranteed to be in whatever register your ADC stores it in". There can be more processing steps between conversion and availability on the digital interface. Digital filtering to implement a 60Hz notch would be quite common1. But these steps aren't making use of the analog circuitry, so they can be performed in parallel with acquisition of the next scheduled sample, and they don't affect the maximum sampling rate. Difference between throughput and latency.


Note that some ADC topologies such as successive-approximation will have separate sampling and hold/convert phases, while others such as sigma-delta won't.


1 Not so much for the >1Msps speeds considered in the question. But there are many other reasons to do digital filtering besides eliminating the grid frequency, and many of these other reasons do apply for high rate ADCs.

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So, let's assume that I have a conversion time (not sampling time, let's not get confused!) of 0.3 us and I declare ADC_BUF_LEN = 1024 samples .. does that mean that the ADC will take 0.3 us*1024 = 307 us to convert all these samples to digital values? In other words that my buffer of 1024 elements will be filled after 307 us.

No. This means that from the time the A/D conversion starts for any given sample, it will be 0.3 microseconds before the read A/D value guaranteed to be in whatever register your A/D puts this in.

When collecting more than one sample, there will be more overhead in the process.

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    \$\begingroup\$ Conversion time may or may not be a lower limit on the sample period. It depends on how pipelined the ADC is. \$\endgroup\$
    – Dave Tweed
    Commented Nov 10, 2023 at 18:28
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You are probably concerned with 'latency'.

A flash ADC will usually output a digital version of the input within a clock cycle.

A successive sampling ADC may consist of several stages, where a coarse initial stage makes a conversion of a few bits. This conversion drives an accurate DAC, and the difference between the input and the DAC is then amplified and sampled by a second stage. This may go on for three or four stages, and then the outputs from all the stages may need to be error corrected against each other. The latency of this type of ADC converter may be many cycles.

Generally, where the latency is several clock cycles, or not obvious from the design of the ADC, it will be clearly specified in the data sheet.

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