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I am designing a board for a 0.8 mm pitch large BGA component. I will be using via-in-pad. There are some differential pairs that need to escape the pin field. The smallest my board house can do (without turning to their expensive "advanced" process) is 3 mil trace / 3 mil space. The smallest vias they can drill are 7.9 mil and the hole-to-cu clearance is 8 mil. With vias spaced 31.496 mils apart, the 3/3 diff pairs cannot fit (7.9mil hole + 16 mils of clearance + 3 + 3 + 3 (trace/space/trace) = 32.9).

A solution to this would be to put alternating rows of vias off-center so that there are some rows where the traces will fit. The via and its pad will still be entirely encompassed by the smt pad and it will be filled and plated over, so I think there should be no problem with this strategy? Heres an image to depict what I mean: offset vias in pads

As you can see, only a slight (1.4 mil) offset is needed to get the traces to fit. Two out of every 3 rows will be able to fit traces. Is this a bad idea for any reason? How do PCB designers usually solve the problem of diff pairs out of 0.8mm pitch BGAs? Do they just escape the pin-field uncoupled? How much uncoupled length is acceptable?

Thanks!

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    \$\begingroup\$ If filled and plated, there are no obvious problems. Reliability wise: If not used in automotive/aerospace/defense: No issues - if so, you wouldn't ask as there would be company guides discussed in a myriade of meetings before hand. Go with it. Usually, i go with smaller vias (.15mm instead of .2mm) or laser blind vias (0.1mm) to route the diff traces on the inner layers. Low-Speed GPIO/Debug/LEDs/etc... live on the outer layers. \$\endgroup\$ Commented Nov 11, 2023 at 18:03
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    \$\begingroup\$ Thanks for your input. This is for a space application and unfortunately no large company with established guidelines. What is the concern in that case? \$\endgroup\$
    – jvtnv
    Commented Nov 11, 2023 at 18:48
  • \$\begingroup\$ ”Do they just escape the pin-field uncoupled? ” Have you tried something like Saturn PCB? Won’t give you all the answers but an estimate of how much you can violate the diff pair. \$\endgroup\$
    – winny
    Commented Nov 11, 2023 at 19:22
  • \$\begingroup\$ @jvtnv To be clear: I have no expertise in this field (Automotive only!). The advice i would give you: Talk this through with your board house. Not a E-Mail with some shallow questions. Make them understand this is for a space-application and you need realiability info and layout guidelines from them. IMHO: If they come up with a 50$/pc pcb instead of 35$/pc dont ask but go with it. Nothing worse then reliability issues due to avoidable problems. Im not saying, that your approach is problematic: But, deviating from standards because of minor cost increases requires "gutts" in such applications \$\endgroup\$ Commented Nov 11, 2023 at 19:43
  • \$\begingroup\$ @winny good point, I'll check Saturn PCB for diff pair rule violation tolerance. Thanks! \$\endgroup\$
    – jvtnv
    Commented Nov 11, 2023 at 22:03

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A solution to this would be to put alternating rows of vias off-center so that there are some rows where the traces will fit. The via and its pad will still be entirely encompassed by the smt pad and it will be filled and plated over, so I think there should be no problem with this strategy?

It should be fine, I would also consider making the clearance smaller around the through hole. Also consider the implications of the capacitance changing ever so slightly with the hole being off center which could affect RF signals that are high speed

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  • \$\begingroup\$ Hmm interesting point. I don't know how to analyze the impact of the capacitance difference but I suppose the bottom line would be to make sure the P and N sides of high speed signals are the same. IE dont use an offset via for P and a centered via for N, etc. \$\endgroup\$
    – jvtnv
    Commented Nov 11, 2023 at 18:52
  • \$\begingroup\$ Need EM skills and do paper calcs or 3d FEM, you are dealing with pfs here so if pfs of crud capacitance don't matter then don't worry about it \$\endgroup\$
    – Voltage Spike
    Commented Nov 11, 2023 at 20:35
  • \$\begingroup\$ Thank you for your answer! \$\endgroup\$
    – jvtnv
    Commented Nov 11, 2023 at 22:00
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It's standard practice to offset such vias to create routing channels.

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The exact via drill position on the finished PCB is depending more on manufacturing tolerances than on your deliberate offset. A drill hole in the exact center of a pad is probably rare even when you put it there in the design files. Staying within the manufacturer design rules prevents more major problems during manufacturing that are caused by tolerances. I think your solution is fine.

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How do PCB designers usually solve the problem of diff pairs out of 0.8mm pitch BGAs?

Blind vias will help a lot, and they are usually a relatively cheap addition to multilayer PCBs. Use blind vias to bring out the non-differential signals to the nearest layers. Then the opposite side layers will be unobstructed for routing the differential pairs.

How much uncoupled length is acceptable?

There is no strict threshold, but you can make estimates based on the rise/fall times or frequency of the signal. For example a typical 1 Gbps differential link could have a rise time of 0.2 ns, with electrical length of 12 cm on a PCB (assuming velocity factor 0.5). Based on transmission line properties, at 1/10th of this (1.2 cm) you wouldn't see much effect at all, while 1/4th (3 cm) would already show significant change in wave propagation.

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    \$\begingroup\$ @Uwe Ah, indeed, forgot that. Fixed. \$\endgroup\$
    – jpa
    Commented Nov 13, 2023 at 6:27
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Vertical conductive structures might be a possibility. They allow for denser routing than even via-in-pad, and are made by drilling out a plated slot periodically to transform it into many separate conductive areas:

enter image description here

It's a newer technically that I haven't had a chance to use myself, so check with your board house to see if they can do it.

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