I'm building a synthesizer on an FPGA and I'm having trouble calculating sampling rates. Currently, I'm running a system clock at 98.3 MHz and I want to produce 16-bit audio at the output.

I've got a 4096-value lookup table for a sine-wave DDS module that produces 16-bit audio. This module increments a 32-bit phase by some amount at 98.3 MHz to achieve a desired frequency determined by

$$\text{increment} = \frac{f_\text{desired}}{98.3\,\text{MHz}\,/\,2^{32}}$$

Then I just take the top 12 bits of the phase to index into my lookup table. Is this correct? Now if I run a PWM at $$98.3\,\text{MHz}\,/\,2^{16} = 15\,\text{kHz}$$

I can generate essentially "1 bit" audio in my headphones and it works. This makes sense, since there are 2^(16) possible values that need to be encoded via PWM. Does this mean I can only produce up to 7.5 kHz sounds by Nyquist, or does not apply since this is at the output not sampling an input?

Further, I don't want to use PWM since 15 kHz is in the audible range and its frequency creates audible artifacts (though I could run PWM at some multiple like 30 kHz). Instead, I tried using PDM to produce "1 bit" audio at 15 kHz but just got noise. Is my understanding of the PDM/PWM frequency correct? When does Nyquist apply?


3 Answers 3


You're conflating several different relevant frequencies, and confusing yourself as a result.

First of all, 98.3 MHz is a ridiculously high clock frequency for an audio-output DDS. For music applications, you need a frequency resolution of about 1/100 of a semitone (a factor of 0.01 × (21/12 - 1) = .00059) at about 20 Hz, or 0.012 Hz. If the highest frequency you need to generate is 20 kHz, then you need log2 (20,000 / .012) = 20 bits of frequency resolution. If we make it 24 bits, then you'll need a DDS clock of 0.012 Hz × 224 = about 200 kHz. What this means is if your FPGA clock is 98.3 MHz, you can use the same block of hardware to generate about 500 independent output channels.

Now, how do we turn that data into an audio signal? As you say, you can use the MSBs of a DDS channel to index a wave table, and then add up as many channels as you want to come up with a numerical output sample. These samples are occurring at the DDS sample rate, or 200 kHz.

The next step is to do digital-to-analog conversion on those samples. PWM is a very crude way to do that with a single digital output bit. A much more sophisticated approach is to use a delta-sigma modulator. Either way, the analog hardware is just a simple low-pass filter.

In its simplest form, a Δ-Σ modulator is just another accumulator, very similar to the one in the DDS. You just keep adding the numerical value of the audio sample to the accumulator, and the output bit is simply the "overflow" bit of the adder. In other words, if the accumulator overflows and wraps around, the output is a "1"; otherwise, it's a "0".

The sample rate and width of the Δ-Σ modulator are dictated by your audio specifications. 16-bit resolution means that your accumulator needs to be at least 16 bits wide. And since you want to generate 20 kHz audio, your effective sample rate needs to be greater than 40 kHz. The Δ-Σ modulator's oversampling ratio should be at least 256, which implies a clock rate of at least 10.24 MHz.

So, let's go back and tweak some numbers. An industry-standard sample rate for high-quality professional audio is 48 kHz. Let's make the DDS sample rate to be 4× that, or 192 kHz. If we want to build a DDS with 512 channels, then the system clock rate would end up being your 98.304 MHz. (Is that how you got that number originally?) The Δ-Σ modulator clock would be 48 kHz × 256 = 12.288 MHz.

  • \$\begingroup\$ This is starting to make more sense, I had a feeling I was confusing things. Two questions: why 0.012Hz * 2^(24)? Is this assuming a 24-bit phase accumulator? What if I only have 4096 24-bit samples in my LUT, would I still just use the 12 MSBs to index into it? I know you could interpolate between samples to remove some quantization error \$\endgroup\$
    – Andrew Li
    Commented Nov 12, 2023 at 5:19
  • \$\begingroup\$ And why should the oversampling ratio be at least 256? Is there a quantitative reason related to the width of the audio sample? Or is this just a rule of thumb? \$\endgroup\$
    – Andrew Li
    Commented Nov 12, 2023 at 5:21
  • \$\begingroup\$ RE my first comment: the frequency resolution is 0.012Hz if we run the DDS ~200kHz with a 24-bit phase accumulator. But, if I actually want that frequency resolution at the output, my LUT would also have to map each of the 2^24 phase values to a different waveform value right? \$\endgroup\$
    – Andrew Li
    Commented Nov 12, 2023 at 5:33
  • \$\begingroup\$ OK, that's a lot of questions. In order: 24 bits is just rounding up to a multiple of 8, which tends to make things more convenient. Yes, you still use the MSBs to index your wave table. Yes, 256x is a rule of thumb. I really didn't want to get into the details. \$\endgroup\$
    – Dave Tweed
    Commented Nov 12, 2023 at 13:16
  • \$\begingroup\$ And no, you don't in general need to map all the phase values to a different waveform value. Even if you didn't use the LUT and instead used the MSB of the DDS directly as a square wave output, it would still have the full 24-bit frequency resolution. The output frequency is simply the number of times the DDS "wraps around" per second. Everything after that is just a question of audio fidelity -- harmonic structure and quantization noise. \$\endgroup\$
    – Dave Tweed
    Commented Nov 12, 2023 at 13:17

If you take only the top 12 bits of the phase register, then a 10 bit output is a good match (similar phase error and amplitude error). 98 MHz clocking 10 bit PWM would give you 98 kHz (ish) of output sample rate, enough for audio.

You should look into sigma delta modulation, aka MASH conversion, aka a noise-shaping converter. That would allow you to produce '16 bit' audio over the full 20 kHz bandwidth from as little as 10 MHz top clock rate, so 98 MHz is overkill. All the noise is pushed into a hump centred on half the sample rate, where it's easily filtered by a low order filter. Small amounts of noise 20 kHz and a little higher are simply inaudible.


If you have 15 kHz rate for samples then highest frequency you can reproduce, which requires two samples to alternate, really is 7.5 kHz.

The fact that PWM is used to output the samples does not affect that, it would be same for any DAC.

Which basically means, buy an audio DAC or codec IC and use some standard audio rate it supports, between 32 and 192 kHz.

Which means you can generate DDS output at this rate too.

  • \$\begingroup\$ Makes sense. So if I want 16-bit audio to cover the entire audio spectrum, I would need 2^16 * 48 kHz = 3 GHz clock? That seems unreasonably high. Even to cover all the piano keys you'd need at least up to 16 kHz, which means 1 GHz clock \$\endgroup\$
    – Andrew Li
    Commented Nov 11, 2023 at 19:56
  • \$\begingroup\$ @AndrewLi Your calculations are correct. Hence 16-bit PWM is not used for audio at 48 kHz, as it makes no sense. \$\endgroup\$
    – Justme
    Commented Nov 11, 2023 at 20:15

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