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Let's say we created some gates or something with VHDL. How can I convert that code into those diagrams that show how discrete components (such as transistors and resistors) are connected to each other?

This diagram shows how discrete components are connected to each other, to make an OR gate:

A non-amplifying OR gate built out of resistors and NPN transistors

I know that using software like Quartus, it is possible to convert VHDL code to a diagram, but they are just showing the logical gates. Is there any way to know how real discrete components are being connected to each other using logical gates?

This is what Quartus can export:

enter image description here

I haven't tried this myself, but I have seen a netlist option in LTspice that says it is possible to export the drawings into a netlist, so my guess is that maybe it is possible to convert VHDL code into a netlist and then import that netlist file into LTspice so that we can see what discrete components are behind those gates.

enter image description here

Netlist:

enter image description here

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When you design in an HDL, you are not actually designing circuits. You are designing logic. Another program (typically) then takes this logic and performs the circuit synthesis based on your target technology. Digital circuits are then synthetized from standard cells specific to that technology. If you want to know the exact circuit-level characteristics, you will have to look up data about your technology's standard cells.

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    \$\begingroup\$ You can design circuits in an HDL. Even analog circuits--look at Verilog-A. But you typically do just design the logic and let it get synthesized into something appropriate for the hardware, yes. \$\endgroup\$
    – Hearth
    Nov 15, 2023 at 21:43
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    \$\begingroup\$ Companies like Apple have been using HDL to design their motherboards. If I'm not mistaken Apple uses Verilog. They don't use GUI CAD. HDL end up being much easier to manage at very large scales. Placement and routing may still be done in GUI but design is mostly done in HDL. \$\endgroup\$
    – slebetman
    Nov 16, 2023 at 4:19
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    \$\begingroup\$ Using HDL to describe a board would make sense, especially if some kind of revision control is being used (e.g., git.) Schematics don't lend themselves to that kind of workflow. \$\endgroup\$ Nov 16, 2023 at 18:11
  • \$\begingroup\$ The idea with the system planner software suites is also to unify definitions, so you have a signal at the ASIC HDL level and it maps through the IC and package layout to the PCB and back up again without having to do any manual entry. With thousands of pins on one IC, there's a high oops potential. It also allows co-design and optimization, so you can have the signal come out of the die and package in the best place to make the PCB layout a lot simpler, while juggling all the other constraints like signal integrity. \$\endgroup\$
    – user71659
    Nov 16, 2023 at 21:38
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passive components are being connected to each other using logical gates?

It depends on the process (TTL or a mosfet based design) in an IC. If one is building the gate on the bench then descrete IC's can be used.

Here is an example of a cmos process with fets, typically mostly nmos fets are used because it's a better design. For or gates typically the best construction is a NOR gate with an inverter because it reduces the number of gates and allows for better construction.

enter image description here Source: https://www.ibiblio.org/kuphaldt/electricCircuits/Digital/DIGI_3.html

After the topology is chosen if you want to put this into an IC the design needs to be layed out for slicon processes and etching. Each mosfet needs to be constructed with a gate, source and drain.

enter image description here Source: https://hackaday.io/project/11779-shared-silicon/log/46754-cmos-nor-gate

On an FPGA a gate built out of individual blocks that can be programmed to be any kind of gate:

enter image description here Source: https://www.geeksforgeeks.org/fpga-full-form/#

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  • \$\begingroup\$ In CMOS gates, NMOS and PMOS transistors will typically be equally numerous. A circuit that behaves as any combination of AND and OR gates, with a total of n inputs that each feed one gate, followed by an inverter, will generally be implementable as n NMOS transistors and n PMOS transistors, provided that n isn't so large that propagation delays become a problem [propagation delays increase with the square of n, so if one needed e.g. a 64-input NOR gate, it might best be implemented as sixteen four-input NOR gates, feeding four four-input NAND gates, feeding a four input NOR gate]. \$\endgroup\$
    – supercat
    Nov 16, 2023 at 21:53
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The question mentions VHDL and gate level primitives. However, VHDL doesn't provide support for gate level primitives.

Whereas the Verilog language does support gate level primitives. Gate Level Modeling Part-I has an overview. E.g. see the Transmission Gate Primitives and Switch Primitives sections.

I haven't designed an ASIC, but believe the Verilog gate level primitives are intended to support ASIC design.

While Verilog may be used for FPGA design entry, not all gate level primitives may be supported. E.g. the Xilinx Verilog Primitives documentation contains:

Vivado synthesis supports Verilog gate-level primitives except as shown in the following table.

Vivado synthesis does not support Verilog switch-level primitives, such as the following:

cmos, nmos, pmos, rcmos, rnmos, rpmos rtran, rtranif0, rtranif1, tran, tranif0, tranif1

The following table lists the gate-level primitives that are not supported in Vivado synthesis.

Unsupported Primitives

Primitive Status
pulldown and pullup Unsupported
drive strength and delay Ignored
Arrays of primitives Unsupported
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    \$\begingroup\$ In VHDL, gate-level primitives are provided by vendor libraries, not by the standard. Doesn't mean they are unsupported. \$\endgroup\$
    – Ben Voigt
    Nov 16, 2023 at 15:20
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VHDL is a hardware language that is oriented toward creating logic. It knows about logical functions and connections between them (wires), and not much else. It isn’t inherently aware of transistor-level implementations.

Even if you were to describe a gate in VHDL as instances of transistors, resistors, and other components, HDL-level simulations wouldn’t know how to deal with them. That’s too low-level.

What describes a circuit at the transistor level when using an HDL? That’s the job of synthesis, which happens toward the end of the HDL design compilation process. Synthesis instantiates pre-configured standard cells for gates and connects them. It's these standard cells that have the transistors and other 'passive' circuitry. Post-synthesis output will have something from which you could view / extract a transistor-level description, from which you could extract a Spice deck.

This issue comes up when it is necessary to do a mixed simulation. VHDL-AMS and Verilog-AMS address this, more about that here: Is there an implementation of mixed analog (SPICE) and digital (HDL) simulations?

Note that this would apply to an ASIC flow, using something like Synopsys Design Compiler. Quartus output on the other hand synthesizes to Intel (née Altera) FPGA primitives: LUTs, flops, wires, switch matrices, hardened macros, RAMs, etc. It isn't directly aware of the circuitry inside these, either, but knows how to configure the blocks to implement the logic behavior described in VHDL. So Quartus will tell you what blocks it used and how they're configured and connected, but it will not tell you what's going on at the transistor level - that's Intel’s secret sauce.

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    \$\begingroup\$ It's now Intel Quartus of course, but this answer does a great job of explaining that FPGA reconfiguration takes place at the level of logic cells and not individual transistors. \$\endgroup\$
    – Ben Voigt
    Nov 15, 2023 at 19:38
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    \$\begingroup\$ @dsa: "Intel's secret sauce" -- They keep it secret because that's the proprietary information that gives them an edge over their competitors. Creating high-density FPGAs that also perform well is hard to do! \$\endgroup\$
    – Dave Tweed
    Nov 16, 2023 at 0:39
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    \$\begingroup\$ @dsa: VHDL can also be used in ASIC design, not only creating FPGA configurations. But the original question included some very strong hints that OP was talking about FPGAs, since Quartus can't be used for synthesis of custom ASICs. \$\endgroup\$
    – Ben Voigt
    Nov 16, 2023 at 15:17
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    \$\begingroup\$ @dsa I understand that ASIC synthesis also works from a library of hand-designed blocks. The VHDL synthesizer doesn't work at the level of individual transistors. However, the internal structure of each library block should be documented (both in ASIC and FPGA). It's not impossible to understand the transistor level behavior of the actual hardware. It just isn't very closely connected to the VHDL. \$\endgroup\$
    – Ben Voigt
    Nov 16, 2023 at 16:38
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    \$\begingroup\$ The docs for the ASIC standard cell library I've worked with (e.g., TSMC) don't document the internals. They only give delays, power, area and functional information. The I/O cells may also have IBIS models for use with board- and package-level sims, but not Spice models. \$\endgroup\$ Nov 16, 2023 at 18:03

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