Let's say we created some gates or something with VHDL. How can I convert that code into those diagrams that show how discrete components (such as transistors and resistors) are connected to each other?
This diagram shows how discrete components are connected to each other, to make an
I know that using software like Quartus, it is possible to convert VHDL code to a diagram, but they are just showing the logical gates. Is there any way to know how real discrete components are being connected to each other using logical gates?
This is what Quartus can export:
I haven't tried this myself, but I have seen a netlist option in LTspice that says it is possible to export the drawings into a netlist, so my guess is that maybe it is possible to convert VHDL code into a netlist and then import that netlist file into LTspice so that we can see what discrete components are behind those gates.