I've a homework question about 32-bit cache memories:
For a cache memory that has size 16kB (16384 byte) and blocksize 2 words, state the names and the sizes of each field of the address that comes from the CPU.
My answer is: 3 bits block offset since 2³=8 and 14 bits for the address tag since 2¹⁴=16384. The rest, 15 bits are for the index of the cache. Is my answer correct?
Assuming that the memory is byte addressable, and words are 32 bits, then each cache line is 8 bytes wide, thus requiring a 3 bit byte address.
The next fields cannot be determined without assuming a cache organization, and so the homework problem is indeterminate.
The cache has 2048 lines, but how are they used?
If the cache is direct-mapped, then of the next 29 bits, 11 bits are an index into the cache, and the remaining 18 bits are address tag.
If the cache is fully associative, then all 29 bits are tag.
And everything in between: four-way set associative means there are 11 - 2 = 9 set index bits, and the tag is 18 + 2 = 20 bits. Each set associativity choice divides the 29 bits between tag and index.
