I think a systematic exposition supported by experiments would be a good addition to the other questions. The idea can be revealed in the sequence below.
Building the circuit
Unloaded CE stage
Let's first remove the second stage (Q2). So we consider a classic common-emitter stage that works as a transistor switch. The interesting state of this stage is off; so let's apply zero input voltage Vin.

simulate this circuit – Schematic created using CircuitLab
Because the voltmeter is "ideal", no currents flow through the circuit, and the output voltage is equal to the supply voltage.
Loaded CE stage...
Let's now load the circuit with a significant load (100 Ω). Since we are interested in the voltage across it, and do not want to complicate the circuit diagram, we can apply a small "2 in 1" trick by reducing the voltmeter resistance to 100 Ω (CircuitLab allows this frivolity). Thus the load is "voltage visualized".

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The low-resistance load draws significant current that creates significant voltage drop. Most of the voltage is lost across R1 and little is left for the load.
... diode inserted...
We move closer to the OP's circuit by inserting a diode D between the output and the load. Almost nothing changes because the diode forward-voltage drop is negligible (0.7 V) compared to the supply voltage (10 V).

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... base-emitter junction inserted
We move even closer to the OP's circuit by replacing the diode with the base-emitter junction of the transistor Q2 (or simply disconnecting its collector if the circuit is already configured).

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As we expected, nothing changes because the base-emitter junction of a transistor is just a diode.
Buffered CE stage
Now comes the most interesting moment - we connect the collector to the power supply to see what this "magic" (aka negative feedback) is here. The "diode" becomes a transistor, and immediately begins to restore the disturbed equilibrium. Now it (not the resistor R1) begins to pass a much larger collector current through the load, and thus increases its voltage until it approaches the input (base) voltage. There is a redistribution of the current (current steering) from the base-emitter junction to the collector-emitter section.

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The transistor settles only when it achieves the equilibrium ratio Ic/Ib = β or Ic/Vbe = gm (transconductance). So the Q1 high-resistance (1 kΩ) output is buffered with the Q2 emitter follower that provides the significant load current.
Discharging diode added
High output voltage: But another problem arises if the load is mostly capacitive. When Q1 is off the load capacitance C is charged to the output voltage of the Q2 emitter follower. Apparently the D diode (for now backward-biased) is put in place to prevent something unwanted from happening the next moment...

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Low output voltage: ... when Q1 turns on. Aha, clear... The charged capacitance (represented by the voltage source Vch in the schematic below) is discharged through the diode. Re limits the current.

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Conclusion
The simple NPN emitter follower is an open-emitter stage that can only source current. So, when the load is mostly capacitive, a path must be provided for its discharge current. A possible way to do this is through a backward-biased discharging diode.