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I don't understand this. Could someone explain this to me? I have a hard time imagining how it works. Why would the signal line be protected by connecting the diodes this way?

If you get an ESD event that is of high potential, it cannot discharge to ground (reversed biased diode between GND and signal track will stop the flow). And the high potential of the ESD event wants to reach ground and not VCC, I assume? Because I assume it wants to 'close the loop.' and discharge any energy. Or can it discharge in the VCC?... Are there any way to close the loop from VCC?

And if you get an ESD event that is of low potential... So then the data line would be negative in respect to ground. Then, would the current come from GND?... From the forward-biased diode from GND? Or?.. because this is normal diodes and TVS diodes. correct?

This is a quote from the page that I link to below

Signal diode arrays can also be used in digital and computer circuits to protect high speed data lines or other input/output parallel ports against electrostatic discharge, (ESD) and voltage transients. By connecting two diodes in series across the supply rails with the data line connected to their junction as shown, any unwanted transients are quickly dissipated"

enter image description here

https://www.electronics-tutorials.ws/diode/diode_4.html

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    \$\begingroup\$ Positive pulses above Vcc+0.7v discharges to Vcc and negative below Gnd-0.7v from Gnd. Consider noise as next source series added to useful signal so it is able to create a current loops through this rails. \$\endgroup\$ Commented Nov 19, 2023 at 22:49
  • \$\begingroup\$ Are you familiar with the concept of a "supernode"? How about the behavior of a voltage source? \$\endgroup\$ Commented Nov 20, 2023 at 2:47

3 Answers 3

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If the data line is more than a diodes drop above VCC, or more than a diodes drop below Gnd, then one of these diodes will conduct and strongly clamp any transients without invoking the clamps inherent in the input of the TTL or CMOS gate.

It has to be this way, because the range in between is the valid signal range.

Clamping to VCC is fine, because all the decoupling caps to Gnd will provide a low impedance path for high frequency transients spikes.

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The diode to Vcc serves another, similar purpose.

It prevents a voltage on the input pin that may exceed the devices absolute maximum ratings, specifically Vin to Vcc, in the case where the device driving the data line powers up before the receiving device does.

Whether or not this is a problem depends on the drive capability of the source and the receiving device specifics (such as the size of aluminum traces and bond wires) and how much current those interconnects can take.

Another way to help ameliorate this problem is with a resistor in series with the data line, so that you can say for sure what the worst case current into an un-powered input would be.

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What's missing in the illustration is the large number of big capacitors between (+)VCC and (-)Gnd. These capacitors are a standard part of digital circuits and are taken as a given.

ESD fault currents through the upper diode will dissipate in these capacitors shielding the digital circuits from large over-voltages.

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