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I really would like to have suggestions and feedback from someone. It's about digital logic, in detail, the Z80 interfacing. In this design, I used a 74HC30 which is a 8-input NAND Gate. I'm using it to detect when the device is addressed by the CPU. Now, since not all the signals can reach the stable state at the same time, noise from the NAND output is expected.

enter image description here

The Z80 asserts the /IOREQ when the address line ( and /M1 ) are stable, hence I'm using this signal as the clock for the D-type Flip Flop.

And it works. Look at the logic analyzer image. The /WAIT is the Q output from the Flip Flop, "out" is the NAND output, and IOREQ is the signal that drives the Flip-Flop's CLOCK input. As you can see, glitches and noise from the "out" is expected, however, /IOREQ is asserted when all the address line are stable ( /M1 too ), so the data we latch into the Flip-Flop is always defined ( and correct ). If the device is addressed, we will latch a 0, otherwise 1.

enter image description here

BUT...

There is another device connected to the Z80, whose firmware forces the Z80 to continuously poll an I/O port until the data is collected. The address where this device is supposed to answer does not collide with the address space I reserved for my device. The effect of such firmware is that my Flip-Flip continuously loads the data, and for some reason bad things start to happen. The /WAIT gets activated when it should not.

To investigate this, I used an oscilloscope.

enter image description here

As you can see, the "DATA" line is Dramatically noisy. The /WAIT has been asserted because the "DATA" was violating the Flip-Flop setup time. As you can see, when /WAIT goes low ( that is also when the rising edge of IOREQ reaches the CLOCK input ), the data is not as high as it should have been.

Without continuous polling, anything is fine.

I can't understand what is wrong. On the logic analyzer seems that the glitches are far enough, but in practice I can count several false /WAIT when a continuous polling is running. enter image description here

I edited this question and added more images for better investigation.

Where the circuit lives.

enter image description here

Signals At the NAND gate inputs. enter image description here

Blue: the NAND gate output, Yellow: the output after passing a trigger Schmitt NOT (74LS14) enter image description here

the Q and /Q flip-flop outputs. For unknown reason, when a pulse is applied to clock input, the Q output drops a little. I suspect that this is because of bad contacts on the breadboard. enter image description here

Yellow the Q output,Blue: the /IOREQ signal after the NOT gate (at the moment a 74LS14 not 74HC04). The wider pulse is because as soon as the Q goes low, the Z80 enters the wait mode, and /IOREQ can't change until it exits it. Here is plain to see that on the pulse, the Q output is affected. enter image description here

I noticed that when the Z80 answers the interrupt, and so stops polling the IO port, things look much better. I suppose that the power supply rail need a dramatic improvement, as well as the ground line... Do you agree with me? enter image description here

Last but not least, two more photos

Here we see the Q output and the 74HC30 output. Since the Q drop occurs on the pulse produced by the /IOREQ, considering that the NAND output is correctly low, the timing are correct. The mess is produced by the noise, and ... enter image description here

... the 74LS14 could resolve the problem, but this needs two NOT gates, so, the question is: Is it possible to reshape a signal using "simple analog parts like diodes"? enter image description here

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  • \$\begingroup\$ Wow, those images took whole seconds to download and view on my PC. Could you not simply take screenshots saved as PNG instead? \$\endgroup\$
    – Tim Williams
    Commented Nov 20, 2023 at 2:46
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    \$\begingroup\$ Mixing LS and HC can make problems, especially when you have glitches. Did you try to replace the 74LS30 with a 74HC30? Or replace the 74HC74 with a 74HCT74, which uses TTL compatible thresholds. -- Anyway, these slow rising edges at the output look fishy. How do the input levels at the 74LS30 look like? Are really only these two HC inputs connected? Did you try to add a pull-up? -- See electronics.stackexchange.com/a/344345/228879 for probably interesting insights. \$\endgroup\$
    – the busybee
    Commented Nov 20, 2023 at 7:44
  • \$\begingroup\$ Very interesting page. What do you mean by "pull-up", the gates are not open-collector ones. \$\endgroup\$
    – ozw1z5rd
    Commented Nov 20, 2023 at 13:29
  • \$\begingroup\$ On paper, with the information provided, the design should work. Therefore, much more information is needed. For example, what is the construction technique? If this is being built on a breadboard socket rather than a PCB, the capacitive loading and crosstalk will be orders of magnitude larger, leading to signal integrity problems. Also, how heavily loaded are the Z80 pins? Is there any buffering? \$\endgroup\$
    – Dave Tweed
    Commented Nov 20, 2023 at 13:44
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    \$\begingroup\$ Oh, you are working on a ZX! :-D Anyway, your bread board has far too few decoupling capacitors. Commonly you provide one for each IC, as near as possible. And the ZX is known for a noisy power. You might want to add an electrolyte type, too. \$\endgroup\$
    – the busybee
    Commented Nov 21, 2023 at 12:22

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