I need to generate an adjustable clock in hdl (verilog) on altera cyclone II fpga using signal probes (blocks that can change their output value through jtag - there is no need to recompile the code). I came up with a solution which uses a counter and a comparator, the output of the comparator being the new clock but this idea creates a very ugly clock (spike) and I was wondering if there is a better solution to this.
On some fpgas (stratix) it is possible to use a reconfigurable pll but this doesn't apply to cyclone II unfortunately.
Thanks for your help
edit: Input clock 24 Mhz. Output clock 1khz - 10Mhz, clock is used for transceiver and receiver blocks, which are simply sending bytes between each other.