I am trying to create a high speed clock on my Spartan 6 Atlys Board. The onboard clonck is 100MHz. I am trying to use an on chip PLL to get a faster clock. I am using a the clocking wizard IP to generate a higher speed clock.
Things work fine as long as my clock frequencies are below 400MHz. If I try to run the output clocks any faster, I see the warning -
"CLK_OUT1 frequency requires that this output clock must drive a BUFFPLL"
The datasheet of the clocking wizard states that
If a clock output requires special buffers like BUFPLL which the wizard does not generate in the design, alert messages are flagged to the user. Feedback for the primitive can be user-controlled or left to the wizard to automatically connect. If automatic feedback is selected, the feedback path is matched to timing for CLK_OUT1.
The Spartan 6 clocking guide mentions BUFPLL as a primitive. I have never done any such designs. How do I proceed. How do I create a BUFPLL in my design? Is this simply beyond the capability of a Spartan 6 or my board?