How do I buffer a high Frequency clock on a Spartan 6?

Question

I am trying to create a high speed clock on my Spartan 6 Atlys Board. The onboard clonck is 100MHz. I am trying to use an on chip PLL to get a faster clock. I am using a the clocking wizard IP to generate a higher speed clock.

Things work fine as long as my clock frequencies are below 400MHz. If I try to run the output clocks any faster, I see the warning -

"CLK_OUT1 frequency requires that this output clock must drive a BUFFPLL"

The datasheet of the clocking wizard states that

If a clock output requires special buffers like BUFPLL which the wizard does not generate in the design, alert messages are flagged to the user. Feedback for the primitive can be user-controlled or left to the wizard to automatically connect. If automatic feedback is selected, the feedback path is matched to timing for CLK_OUT1.

The Spartan 6 clocking guide mentions BUFPLL as a primitive. I have never done any such designs. How do I proceed. How do I create a BUFPLL in my design? Is this simply beyond the capability of a Spartan 6 or my board?

Answer 1

I haven't used Spartan6 specifically, but you should be able to instantiate a BUFPLL (page 52) primitive and feed the output of whatever is generated by the wizard into that.

Page 80 of Xilinx Spartan-6 Libraries Guide for HDL Designs will have the info you need on instantiation.

Answer 2

Anything higher than 300 MHz needs optimal design and environment conditions. Even if frequencies higher than that are observed on the Oscilloscope they would be attenuated and not of the right voltage level.

To achieve higher clock speeds you need to get faster FPGAs (Kintex Series etc.)

Answer 3

Your problem seems to be routing a highspeed clock to io-logic to provide this to an external peripheral. If that is the case you indeed need a bufpll to access the io-banks. you can find an instantiation template for bufplls in your ise enviroment (yellow bulb) on top of your ise controlpanel. you can find it among other usefull stuff like plls and dcms below the clocking tab. copy this into your hdl source code.

do not forget to include the unisim library and that a bufpll can only be driven by port clk0 or clk1 of your pll. frequencies up to 1 ghz as io-clk are possible. although you might also need a oddr primitv, which can also be found in the library ive mentioned.