I have this boolean expression that I got through a k-map twice, once using POS and the other SOP, and I am supposed to implement both minimized f's that I found using only NAND-2 gates but I am very stuck trying to do it. I've tried just taking every term and writing the direct equivalent of it in NAND gates but it's way too big and seems like some parts are repetitive I am not sure. I've tried using Logisim but when it implements it it adds an extra input of 1 I guess to make it work. any suggestions on how to solve this?

This is the expression I need to implement:

f(x1, x2, x3, x4) = ∑(3,5,6,7,10,11,12,13)

this is the minimized SOP expression of f:

(x1')x3x4 + (x1')x2x4 + (x1')x2x3 + x1x2(x3') + x1(x2')x3

and minimized POS expression of f:

(x2+x3) (x1+x3+x4) (x1+x2+x4) ((x1')+(x2')+(x3'))

This is the circuit I got for the first expression of Logisism:

enter image description here

Second circuit for POS expression of f:

enter image description here

this is the circuit I tried drawing by hand using just direct NAND equivalents that i mentioned before:

enter image description here

  • \$\begingroup\$ (FWIW, I don't see redundancy in "the Logisim diagrams". All "synthesised 3-input NAND"s look the same, as do all 2-input ORs.) \$\endgroup\$
    – greybeard
    Nov 23, 2023 at 4:56
  • \$\begingroup\$ the redundancy I was referring to would be in the hand-drawn one, not the one created by Logisim. \$\endgroup\$ Nov 23, 2023 at 10:11

2 Answers 2


I've tried using Logisim but when it implements it it adds an extra input of 1 I guess to make it work.

The reason Logisim does this is because it needs to invert the inputs. So to create an inverter (NOT gate) from NAND gates, it keeps one input as always on or High. (Alternatively, it will tie both inputs together to achieve the same task).

The truth table would look like the following (A = 1 always in this case):

A B Out
1 0 1
1 1 0

When it comes to software and sim tools, they follow a specific set of rules. They won't always give you what you need so it takes some extra work to refine the answer into what you may need.

A good approach would be to spend some time looking at the parts you feel are repetitive and combining/rearranging/adding/removing gates to try reducing the number of gates.

If you are able to, using more than NAND gates may reduce complexity greatly.

  • \$\begingroup\$ Thank you for your answer, so is there a way to make it so that it doesn't add that extra 1 input? I do have to use only NAND-2 gates which I understand does make it a lot more complex, I've tried doing it without a restriction on gates which as you said comes out less complex, and then maybe translate it into NAND that way but gets a bit too confusing. \$\endgroup\$ Nov 23, 2023 at 9:22
  • \$\begingroup\$ @SalmaMostfa Assuming the extra input is the vertical one set to always be on, then I would suggest tying both inputs to your A line, B line, C line, etc. like you did in your drawing. When one applies restrictions to problems like this, sometimes you can only make it so simple. Do you know that there is a simpler form? or are you asking this out of curiosity? \$\endgroup\$
    – Pxl
    Nov 23, 2023 at 16:44
  • \$\begingroup\$ I was almost certain that there could be a simpler form, but I've figured it out now I was able to narrow down the SOP form to a 27 NAND gate circuit and the POS form to 25, I just retried drawing it by hand a few times with just translating every term directly to its NAND gate equivalent and then canceling out all redundant NOT gates. Thank you so much for your help. \$\endgroup\$ Nov 24, 2023 at 16:18
  • \$\begingroup\$ @SalmaMostfa I am glad that it worked out for you! \$\endgroup\$
    – Pxl
    Nov 24, 2023 at 16:22

In the sketch, there are funny/redundant pairs of inverter-connected NANDs in series where the labels are.
Other than that, it looks pretty much "Logisim's SoP diagram".


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