What is the main difference between RTL and HDL? To be honest I searched / googled it yet people are divided in their opinions. I remember one saying that HDL is the computer language used to describe a digital circuit and when it is synthesizable, then it is considered RTL.
HDL is the catch all name for all hardware definition languages (Verilog, VHDL, etc.) in the same way Object Oriented can refer to C++, Java, etc.
RTL on the other hand is a way of describing a circuit.
You write your RTL level code in an HDL language which then gets translated (by synthesis tools) to gate level description in the same HDL language or whatever your target device/process will take.
Let me give you an example. Here is a line of Verilog (HDL) describing a mux in RTL:
assign mux_out = (sel) ? din_1 : din_0;
Your synthesis tool can take that and convert it to a set of logic gates, or just a mux macro that is supported by your end device. For example it might instantiate a mux macro
mux u3 (mux_out, din_1, din_0);
In both cases you can feed the same inputs to the block (RTL, or gate-level) and your output should be the same. In fact there are tools that check the output of your synthesis against your RTL code to make sure the tool didn't accidental optimize or change something during synthesis that caused a mismatch. This is called Formal Verification.
For a variety of reasons, interoperability, ease of change, understandability you write your description of the digital circuit as RTL, instead of gate-level.
RTL (Register-transfer level) is a level of abstraction that you are writing in. The three levels I refer to are Behavioural, RTL, Gate-level.
Behavioral has the highest layer of abstraction which describes the overall behavior and is often not synthesizable, but is useful for verification.
RTL describes the hardware you want by implying logic. defining flip-flops, latches and how data is transfered between them. This is synthesizable, synthesis may alter/optimize the logic used but not behavior. Switching muxes for gates etc some times inverting signals to better optimize the design.
Verilog RTL implying a flip-flop:
logic a; //logic is SystemVerilog, could be a 'reg' logic k; // Driven by RTL not shown always @(posedge clk or negede rst_n) begin if (~rst_n) begin a <= 'b0 ; end else begin a <= k ; end end
Combinatorial Bitwise operators :
logic [1:0] n; logic [1:0] m; logic [1:0] result; assign result = n & m ;
Gate level is a design using the base logic gates (NAND, NOR, AND, OR, MUX, FLIP-FLOP). It does not need to be synthesized or is the output from synthesis. This has the lowest level of abstraction. it is the logic gates that you will use on the chip, but it lacks positional information.
Gate level Verilog (same function as above):
wire a; wire k; DFFRX1 dffrx1_i0 ( .Q (a), //Output .QN( ), //Inverted output not used .D (k), //Input .CK(clk), //Clk .RN(rst_n)// Active Low Async Reset );
wire [1:0] n; wire [1:0] m; wire [1:0] result; AND2X1 and2x1_i0 ( .Y( result), .A( n ), .B( m ) ); AND2X1 and2x1_i1 ( .Y( result), .A( n ), .B( m ) );