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What is the main difference between RTL and HDL? To be honest I searched / googled it yet people are divided in their opinions. I remember one saying that HDL is the computer language used to describe a digital circuit and when it is synthesizable, then it is considered RTL.

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HDL is the catch all name for all hardware definition languages (Verilog, VHDL, etc.) in the same way Object Oriented can refer to C++, Java, etc.

RTL on the other hand is a way of describing a circuit.

You write your RTL level code in an HDL language which then gets translated (by synthesis tools) to gate level description in the same HDL language or whatever your target device/process will take.

Let me give you an example. Here is a line of Verilog (HDL) describing a mux in RTL:

assign mux_out = (sel) ? din_1 : din_0;

Your synthesis tool can take that and convert it to a set of logic gates, or just a mux macro that is supported by your end device. For example it might instantiate a mux macro

mux u3 (mux_out, din_1, din_0);

In both cases you can feed the same inputs to the block (RTL, or gate-level) and your output should be the same. In fact there are tools that check the output of your synthesis against your RTL code to make sure the tool didn't accidental optimize or change something during synthesis that caused a mismatch. This is called Formal Verification.

For a variety of reasons, interoperability, ease of change, understandability you write your description of the digital circuit as RTL, instead of gate-level.

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    \$\begingroup\$ Nice answer, just a further refinement ... RTL assumes a given design style - logic cloud, register, logic cloud , register etc. which implies synchronous (clocked) design. IF you were coding in your hdl for clockless (asyncronous) design your synthesis tool might use something other than RTL. \$\endgroup\$ – placeholder May 12 '13 at 21:36
  • \$\begingroup\$ ,,In fact there are tools that check the output of your synthesis against your RTL code to make sure the tool didn't accidental optimize or change something during synthesis that caused a mismatch. This is called Formal Verification.'' No, this is not. This is called Logic Equivalence Checking or Formal Equivalence Checking. The Formal Verification is rather process of proving (using mathematical methods, without simulation/test benches) that your hardware description really describes the behavior it was intended to describe. \$\endgroup\$ – Al Bundy Apr 2 at 6:50
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HDL (Hardware description Language) is the type of language used, Verilog/VHDL versus a non-HDL javascript.

RTL (Register-transfer level) is a level of abstraction that you are writing in. The three levels I refer to are Behavioural, RTL, Gate-level.

Behavioral has the highest layer of abstraction which describes the overall behavior and is often not synthesizable, but is useful for verification.

RTL describes the hardware you want by implying logic. defining flip-flops, latches and how data is transfered between them. This is synthesizable, synthesis may alter/optimize the logic used but not behavior. Switching muxes for gates etc some times inverting signals to better optimize the design.

Verilog RTL implying a flip-flop:

logic a;              //logic is SystemVerilog, could be a 'reg'
logic k;              // Driven by RTL not shown
always @(posedge clk or negede rst_n) begin
  if (~rst_n) begin
    a <= 'b0 ;
  end
  else begin
    a <= k ;
  end
end

Combinatorial Bitwise operators :

logic [1:0] n;
logic [1:0] m;
logic [1:0] result;

assign result = n & m ;

Gate level is a design using the base logic gates (NAND, NOR, AND, OR, MUX, FLIP-FLOP). It does not need to be synthesized or is the output from synthesis. This has the lowest level of abstraction. it is the logic gates that you will use on the chip, but it lacks positional information.

Gate level Verilog (same function as above):

wire a;
wire k;
DFFRX1 dffrx1_i0 (
  .Q (a),   //Output
  .QN( ),   //Inverted output not used
  .D (k),   //Input
  .CK(clk), //Clk
  .RN(rst_n)// Active Low Async Reset
);

Combinatorial

wire [1:0] n;
wire [1:0] m;
wire [1:0] result;

AND2X1 and2x1_i0 (
  .Y( result[0]),
  .A( n[0]     ),
  .B( m[0]     )
);
AND2X1 and2x1_i1 (
  .Y( result[1]),
  .A( n[1]     ),
  .B( m[1]     )
);
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  • \$\begingroup\$ If one were to design a circuit as MyReg[7..1] := MyReg[6..0]; MyReg[0] := SerInput; MyReg.Clk = SerClk; MyReg[7..0].AR = !InBus[7..0] & Load; MyReg[7..0].AP = InBus[7..0] & Load; (an asynchronous parallel-load shift register which could be implemented on a Xilinx 9536 CPLD using blocks with async reset/preset) would that be considered RTL or gate-level? \$\endgroup\$ – supercat May 14 '13 at 17:01
  • \$\begingroup\$ RTL, gate level would look like AND(.a(),.b()) OR(.a(),.b()) purely logic gates being hooked up. I am under the impression that RTL is anything you intend to synthesise, even combinatorial circuits as you are still describing the change in data, but not the logic gates directly. \$\endgroup\$ – pre_randomize May 14 '13 at 20:41
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    \$\begingroup\$ Sorry I do not follow, Will try to clarify. RTL implies a flip-flop. Gate-level instantiates a flip-flop. For simple circuits then hooking up a bunch of logic gates might be simple. but may not be power area efficient. An Atom Processor has 47 million transistors which is around 10 million NAND2 equivalents. Would you want to define and debug 10 million hand wired gates ? This is the advantage of abstracting a little bit we can study and debug the intended behaviour. \$\endgroup\$ – pre_randomize May 15 '13 at 7:38
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    \$\begingroup\$ Suppose one were trying to specify a 74HC74 in an HDL. There are a variety of ways one could synthesize such a device using a combination of combinatorial logic, synch-only flops, and transparent latches, but I can't figure any implementation which doesn't either involve race conditions or create behavioral anomalies which would not exist with hardware primitives (e.g. if D and Q are high, a runt pulse on CP or /SD should have no effect, but in the implementations I can figure such pulses could cause metastability and/or an output glitch). \$\endgroup\$ – supercat May 15 '13 at 15:20
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    \$\begingroup\$ How are you creating MyLatch is it an instantiated base cell or an implied latch. If you instantiate the gate it is gate level If you imply it, it is RTL. The gate level library will have timing associated with it for modelling race conditions/glitches etc. RTL simulations run with ideal components. \$\endgroup\$ – pre_randomize May 17 '13 at 21:55

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