I have implemented this circuit in the hardware. The desired pulse output across 2 Ω is 28 V output, minimum 10 A output current with 100 kHz frequency and 10% duty cycle. The drain pulse is not switching at the desired frequency. The switching pulse is obtained for frequencies in the range of MHz.
In simulation, I have used different part numbers as I didn't have the Pspice models for the parts used in hardware. What is the reason for the signals across Vbe and Vce to be as shown in the figures above. Is that right? Can we obtain a negative voltage across Vbe?
Also, I had a doubt to check as to what happens if the diode is not present. I have observed that the BJT connected across the gate and source of the MOSFET, when in cutoff, the collecter-emitter open voltage is very small. Then, in that case I doubt if the BJT is really going into cut-off. How much should the Vce be when the BJT is in cut-off?
Overall, I feel that the gate driver circuit has some issues. Please suggest a better circuitry to achieve the desired output.
