So I'm currently writing VHDL code for a 7-segment display that will display (0-F) once each second. I have almost everything done, the only thing I'm stuck on is the controller.

I need to have 4 buttons, the first starts the counter, the second stops it, the third increments it by one, and the last one resets it back to 0 (I already have the last one done, I just need the first three)

Here is my overall code (Note that Problem 2 component is my counter):

entity SSD is
port (
   seg : out std_logic_vector (6 downto 0);
   an3 : out std_logic;
   btn1, btn2, btn3, btn4 : in std_logic;
   clk : in std_logic);
    end SSD;

    architecture Behavioral of SSD is

    component hex7seg is
    port (
        x : in std_logic_vector (3 downto 0);
        a_to_g : out std_logic_vector (6 downto 0));
    end component;

    component Problem2 is
    port (
        clr : in std_logic;
        ce : in std_logic;
        clk : in std_logic;
        b : out std_logic_vector (3 downto 0);
        tc : out std_logic);
    end component;

component clkdiv is
port (
    rst : in std_logic;
    clk : in std_logic;
    clkout : out std_logic);
end component;

component controller is
port (
    start : in std_logic;
    stop : in std_logic;
    inc : in std_logic;
    rst : in std_logic;
    clk : in std_logic;
    run : out std_logic);
end component;

signal b : std_logic_vector(3 downto 0);
signal run : std_logic;
signal clk_1sec : std_logic;
signal tc : std_logic;


U1: hex7seg port map (x => b, a_to_g => seg);

U2: Problem2 port map (clr=>btn4, ce=>run, clk=>clk_1sec, b=>b, tc=>tc);

U3: controller port map (start => btn1, stop => btn2, inc => btn3, rst => btn4, clk => clk_1sec, run => run);

U4: clkdiv port map (rst => btn4, clk => clk, clkout => clk_1sec);

an3 <= '0';

end Behavioral;

Here is what I have so far for the controller code:

entity controller is
    Port ( start : in  STD_LOGIC;
           stop : in  STD_LOGIC;
           inc : in  STD_LOGIC;
           rst : in  STD_LOGIC;
           clk : in  STD_LOGIC;
           run : out  STD_LOGIC);
end controller;

architecture Behavioral of controller is

    run <= '1';

end Behavioral;

I'm not really sure where to go from there to get the other 3 buttons working, any help or direction would be greatly appreciated.

  • 2
    \$\begingroup\$ -1 for little effort. Please try to distill your confusion into an answerable question, instead of just putting up a half finished homework assignment and asking for the rest. Can you describe exactly what has you stuck, or what you don't understand? \$\endgroup\$
    – Tim
    May 12, 2013 at 21:16
  • \$\begingroup\$ I'm just not sure what would make the counter start and stop in terms of code. I'm able to get the counter to reset with one of my buttons, but I am unsure of how to make it pause and resume. Sorry if it seems like I'm just looking for code, I just don't know where to start with getting the start and stop accomplished \$\endgroup\$ May 12, 2013 at 21:22
  • \$\begingroup\$ Well, on every clock cycle, you want your counter to either a) increment, or b) keep the same value. Perhaps when the pause button is pressed you could put a 1 in a pause register. Then on positive edge of clock you look if the pause register is set, and choose to increment or stay the same based on that. You can clear the pause register when the resume button is pressed. Hope that gives you some idea of what to go on. \$\endgroup\$
    – Tim
    May 12, 2013 at 21:29

1 Answer 1


I haven't coded in VHDL in a long time -- I don't know why they still teach it, they should teach Verilog -- but the answer below still applies.

Your counter needs to have the following inputs:

  1. Clock - you already have it
  2. Increment - if that signal is high the counter should increment by one on the next rising edge of the clock
  3. Clear - you already have it, it should reset the count back to zero
  4. Counter Enable - Let's you pause/unpause the counter, make sure 'increment' still works even if Counter Enable is zero.

Your controller takes in 4 button inputs and generates 3 outputs. For buttons 3 and 4 it detects a rising edge of the input and generates a pulse for 1 clock cycle, i.e.

          ____    ____    ____    ____
clock:  __|  |____|  |____|  |____|  |
input:  _______|                  |_____
output: __________|  |__________________

The "counter enable" output of the controller is controlled by buttons 1 & 2. A rising edge on button 1 sets it high and a rising edge on button 2 clears it to low. In effect the counter enable is controlled by an SR latch where the S signal is button 1 and R is button 2.

You then connect the 3 outputs of the controller to your counter (Problem 2).

  • 5
    \$\begingroup\$ Why shouldn't they teach VHDL? A significant portion of the world of logic design is done with it. And it's a lot harder to shoot yourself in the foot when you're a newbie than with Verilog. \$\endgroup\$ May 13, 2013 at 15:40
  • 2
    \$\begingroup\$ Not just when you're a newbie. And I doubt that my synthesisable VHDL would translate at all well to Verilog! \$\endgroup\$
    – user16324
    May 13, 2013 at 19:37
  • 2
    \$\begingroup\$ "Most synthesis tools don't support vhdl"? That is a very UNTRUE statement, care to support it? \$\endgroup\$ May 14, 2013 at 0:13
  • 1
    \$\begingroup\$ I'd say that most major FPGA synthesis tools support VHDL: Synplify Pro, Altera Quartus II, Xilinx ISE, Lattice Diamond and ispLEVER, LeonardoSpectrum, ModelSim (since you mentioned NCSim). From the datasheets of the (mostly) ASIC tools you mention, all of them support VHDL, I could not find any official statement about not fixing VHDL related bugs. \$\endgroup\$ May 14, 2013 at 1:15
  • 1
    \$\begingroup\$ To some extent: Synplify Pro, Quartus II, Aldec Active-HDL, ModelSim, all support VHDL-2008. Xilinx ISE doesn't support VHDL-2008, but they make sure their new stuff works with at least VHDL-93, such as newer bus functional models. A recent (2012) Vivado release note has the non-specific: "System Verilog and VHDL language support enhancements". So I think VHDL is alive and supported in not only in the "compiles" sense. For the fabless company you worked for it was true, but I don't think it is true in a broader way, and certainly not in the FPGA "wild" world. \$\endgroup\$ May 14, 2013 at 2:18

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