# What is the theoretical maximum capacity of 72-pin RAM modules?

I'm asking, because the information on Wikipedia is extremely lackluster, perhaps even incorrect.

This is my current understanding:

A 72-pin module has 12 address pins, 4 CAS, and 4 RAS pins. (For simplicity, I'm disregarding parity here). Data is 32 bit wide (4 bytes).

A read cycle consists of applying a 12-bit row-address, pulling a CAS pin high, then applying a 12-bit column-address, and pulling one of the RAS pins high.

In effect, a memory location address is 24 bit wide (12 bit for row, and 12 bit for column). So that's 2^24 = 16777216 = 16M memory locations per one combination of CAS/RAS selection.

However each module allows up to four CAS and RAS pins. Each time, only one one of each must be strobed. So one out of 4 CAS and one out of 4 RAS, giving 16 combinations.

With those, that's the 16M locations from above, times the 16 combinations of CAS/RAS strobes, resulting in 16M × 16 = 256M locations.

Since each location applies a 32-bit word on the data bus, that results in 256M × 4 byte = 1024MB (or 1GB) of capacity. That's the theoretical maximum capacity I understand is possible.

On the Wikipedia page, it's however mentioned that only a maximum of 128MB was ever possible (32M locations).

I don't understand how they arrive at that conclusion, but that aside, I wonder if there's something wrong with the way I understand addressing. I am aware, that smaller modules either disregarded the MSBs of some of the address pins, or used only two RAS pins, but that doesn't answer the question for the theoretical maximum. I'm also aware, that many mainboards didn't support modules larger than 128MB (or even 64MB). As another reference I used the datasheet for one of those modules made by Micron Technology Inc.

Did you look at the functional block diagrams in that datasheet?

The four CAS# lines are used to enable the four bytes of a 32-bit word.1 Furthermore, two RAS# lines are used for each 32-bit word. This is one "bank" of memory, and the other two RAS# lines can be used to enable a second bank.2

In that particular datasheet, they're only using 11 address bits, so they can address 222 words per bank for a total of 16 or 32 MB.

If you have a module that uses all 12 address bits, then you can address 4× as much memory, which is 64 MB for one bank or 128 MB for two banks.

Also, the basic timing sequence is:

2. Assert RAS# low.
3. Apply column address. If write cycle, also assert WE# low and drive the data.
4. Assert CAS# low.
5. If read cycle, capture data after appropriate delay.
6. Negate RAS# and CAS# (high).

1 This is what makes the memory byte-addressable without having to do read-modify-write cycles.

2 I believe it was done this way so that each RAS# and each CAS# line would be connected to at most 4 physical chips. It also means that the module can be wired up directly to a 16-bit bus as two or four 16-bit banks.

• I did look at the block diagram, but I was kinda confused by how the lines go under the memory blocks. Just to be clear: all CAS and either RAS 0+2 or RAS 1+3 are strobed during a read/write cycle? Commented Nov 25, 2023 at 6:36
• Yes, exactly right -- for 32-bit memory cycles. The individual CAS# lines is what makes the memory byte-addressable without having to do read-modify-write cycles. Commented Nov 25, 2023 at 12:11
• Hmm, I don't quite get how the byte addressing works. If I only select the second byte (by strobing only CAS1) then only part of the data bus (bits 8-15) would be valid, the rest invlaid. Wouldn't they? It's not like the addressed data is right shifted to bits 0-15, is it? Commented Nov 25, 2023 at 15:55
• @polemon: No, the data isn't shifted. The CPU understands the layout of memory as 32-bit words, and does any required shifting internally. Commented Nov 25, 2023 at 23:48
• @polemon: How many and what size cycles will be needed to perform longword transferred to the CPU shows how per-byte masking works on a 4-byte bus in a ColdFire CPU. (Semi-related for modern CPUs with cache: Are there any modern CPUs where a cached byte store is actually slower than a word store? - fun fact, most non-x86 CPUs do commit byte stores to cache with an RMW, if they can't coalesce in the store buffer. But x86 CPUs typically support unaligned and byte stores with full speed, probably with parity L1d not ECC) Commented Nov 26, 2023 at 6:33

Although you could build a CAS/RAS decoder, that would introduce latency: you'd need the encoded CAS/RAS information before deciding which set of chips to address, and which physical CAS/RAS signal to generate.

In actual implementation, the external CAS/RAS signals are connected to a CAS/RAS on physical chips. 24 address bits * 4 byte width * 2 physical banks (one on each side of the module) = 24+2+1 = 27 = 128MB. You could build a 256 byte / 4 bank module using multi-layer wiring, but I don't know that I ever saw one.