Altera CPLD EPM570 series have four global clocks(GCLK0-GCLK3)，I want to assign two clock sources to CPLD: one from oscillator and one from a MCU. From "GLOBAL SIGNAL" part of "MAX II Architecture"MAX II Architecture, i get confused.the structure is shown below: why does CPLD have four clock output? I think it should only have one output connecting one of four global clocks. Does it mean that four clock output will serve different logicals? and is it safe to assign different clock sources to different GCLKx?
Multiple clocks are often needed because several parts of the CPLD (or FPGA for that matter) will be programmed with separate functionality that operates asynchronously from other parts using separated clock domains.
Other times some clocks will be generated from an external clock source using one of the specialty clock generator chips that created different clocks that have defined phase relationships. These can be leveraged in different parts of the CPLD/FPGA in a way to optimize the operational behavior of the chip programming.
It is perfectly safe to have different parts of the CPLD / FPGA using different clocks. Your challenge as the designer is to use extreme care to keep each circuit confined to its own clock domain. And if it turns out to be necessary for some logic to make a crossing from one clock domain to another that you apply the necessary design rigor to apply the necessary clock synchronization circuits to the crossing paths to ensure that the resulting logic is stable and not subject to metastability problems.
Although logic design is easiest in cases where there's a master clock signal that is fast enough to capture all events of interest using entirely synchronous logic, such a state of affairs does not always exist, especially with CPLDs. As a simple example, one may wish to have a CPLD that acts like a serial-to-parallel shift register, but instead of using a separate "strobe output latches" signal, one may wish to have the output data latch strobe if there are two consecutive rising edges on the data wire while the clock wire sits low. On such a design, the shift-register stages would be strobed by the clock input, but there would be a pair of latches which are strobed by the data input and asynchronously cleared by the clock input (one would latch "1", and the other would latch the first); the output of the second latch would then strobe the output data latches. Note that the circuit may have no other clocks available to it other than the "clock" and "data" inputs, but must be able to detect and count edges that occur on either. Note also that while it is necessary to use synchronization logic (and beware of metastability) if one is crossing between clock domains that have no known timing relationship, there are many useful situations where one may have signals whose edges have to be detected individually (requiring them to be used as distinct clocks), but which can be guaranteed at the source not to change simultaneously.
With regard for why the mux is drawn as it is, I would interpret the drawing as representing four separate 8-input muxes, so that the four global clock wires could be fed by the four clock input pins, by four pieces of logic, or by some combination of clock input pins and internal logic. I don't know whether the device actually has four separate 8-input muxes, or whether it just includes enough multiplexing logic to allow all functionally-distinct arrangements of clock inputs and outputs. If the logic blocks that feed the muxes are fully interchangeable, and the master clock buses are as well, I would think one could replace the four eight-input muxes with two-input muxes, each taking one master clock input pin and the output of one logic block. Any master clock input pins which are used as clocks should be passed through by their mux. The other muxes should support logic outputs. If the total number of clocks needed is less than four, one could map the logic blocks to feed muxes that weren't passing input-pin signals.