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I am relatively new to ASIC design. I have experience at RTL design level and have successfully developed designs on FPGA's, but the ASIC world is still new to me. I don't have access to commercial tools, but I'm working my way into SiliconCompiler (Yosys, OpenROAD, etc.).

What is the point of tools like OpenRAM or Memory Compiler e.g. from Synopsys (I think both do basically the same) to instantiate SRAM's?

Why is it not possible (or rather common) to simply include something like that Simple Verilog Single Port Ram in a design and use it as SRAM?

In the course of the design flow (synthesis -> physical design), the tools take care of instantiating this module as memory.

I did this for example, and Silicon Compiler was able to realize this design (generating a gds file) without using a memory compiler (see the picture).

Layout of my 8-Bit Processor

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    \$\begingroup\$ Ultimately this is really a question of "Why use a SRAM when I can just synthesize my block RAM storage out of flip-flops?". If you don't know why SRAM/DRAM has advantages, that may be a better place to start asking. \$\endgroup\$
    – W5VO
    Commented Nov 28, 2023 at 20:28
  • \$\begingroup\$ @W5VO: That's not the question at all. "the tools take care of instantiating this module as memory" excludes "synthesize storage out of flip-flops". \$\endgroup\$
    – Ben Voigt
    Commented Nov 29, 2023 at 15:36
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    \$\begingroup\$ @BenVoigt If you look at the layout, if there was some memory in code, it was synthesized into flops. There is no memory array. While I haven't had the pleasure of using a memory compiler, my assumption is that the memory compiler takes your memory requirements as an input and generates a hard macro to be instanced by P&R and the HDL. I don't know what Synopsis does with recent processes, maybe it's fully integrated now. \$\endgroup\$
    – W5VO
    Commented Nov 29, 2023 at 16:42
  • \$\begingroup\$ @W5VO: I don't know what Synopsys does either, but I do know that HDL compilers for FPGAs are perfectly capable of recognizing memories in behavioral HDL and triggering the synthesizer to instantiate block RAMs instead of logic cells, just as effectively as if you used the vendor-specific megafunction library, so if the HDL compilers for ASICs aren't able to automatically launch the RAM layout processing that seems like an optimization bug. \$\endgroup\$
    – Ben Voigt
    Commented Nov 29, 2023 at 16:54
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    \$\begingroup\$ @BenVoigt First off, this is definitely an area where FPGA != ASIC. If I needed 99kbits of memory, it's one thing to say "I'll implement that with my existing 128kbit array that I have in my library." What a memory compiler can do is generate arbitrary* shape arrays that then have sufficient design information (e.g. timing files, verilog, LEF/DEF, netlists, layouts) to implement it successfully in a digital ASIC. Generally this is a computationally intensive task and you don't want it to be in your main synthesis loop. \$\endgroup\$
    – W5VO
    Commented Nov 29, 2023 at 17:55

2 Answers 2

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Memory compilers are needed because the physical structure of memories go beyond the Boolean logic most synthesis tools are designed to work with. They are also very dependent on the target ASIC technology used to implement them, usually in CMOS primitives instead of logic gates.

And since they are very large, regular structures, they can be generated by simple replication rather than feeding massive sets of logic equations to a synthesis tool. That gives you better results (area/timing) versus what can be achieved with pure logic equations.

Using synthesis tools provided (or recommended) by the ASIC vendor may autmatically map SRAM to their target technologies.

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  • \$\begingroup\$ Unsupported claim that synthesis tools only handle logic and don't recognize memory behaviors and infer RAM \$\endgroup\$
    – Ben Voigt
    Commented Nov 28, 2023 at 16:25
  • \$\begingroup\$ @BenVoigt, didn't claim that all don't, but most open source synthesis tools don't. \$\endgroup\$
    – dave_59
    Commented Nov 28, 2023 at 16:43
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Memory compilers offer the following benefits as compared to memory designs consisting of arrays of flip-flops:

  • Smaller area
  • Faster speeds
  • Lower power

The Synopsys link mentions this as well:

Optimized for low power, high performance and high density

They also save you the effort in place-and-route, static timing analysis and layout since the compilers generate all that for you.

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    \$\begingroup\$ The question appears to be asking what is the advantage of a separate tool, when the HDL compiler is perfectly capable of inferring RAM (so it won't synthesize to flip-flops). It explicitly says "In the course of the design flow (synthesis -> physical design), the tools take care of instantiating this module as memory." \$\endgroup\$
    – Ben Voigt
    Commented Nov 28, 2023 at 16:23
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    \$\begingroup\$ @BenVoigt: I saw the synthesizable RTL Verilog code in the "Single Port Ram" link and assumed the Verilog code would be synthesized into flip-flops. \$\endgroup\$
    – toolic
    Commented Nov 28, 2023 at 19:06
  • \$\begingroup\$ @BenVoigt Exactly thats what I meant! I work right now with the SKY130 PDK and my tool has access to the SRAM Bitcell, so I don't understand why the HDL compiler doesn't directly infer an SRAM (consisting of SRAM bit cells) instead of flip-flops. \$\endgroup\$
    – Nadax
    Commented Nov 29, 2023 at 2:52
  • \$\begingroup\$ @toolic: That's not a new question, it's the one originally asked. \$\endgroup\$
    – Ben Voigt
    Commented Nov 29, 2023 at 15:35

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