I am relatively new to ASIC design. I have experience at RTL design level and have successfully developed designs on FPGA's, but the ASIC world is still new to me. I don't have access to commercial tools, but I'm working my way into SiliconCompiler (Yosys, OpenROAD, etc.).
Why is it not possible (or rather common) to simply include something like that Simple Verilog Single Port Ram in a design and use it as SRAM?
In the course of the design flow (synthesis -> physical design), the tools take care of instantiating this module as memory.
I did this for example, and Silicon Compiler was able to realize this design (generating a gds file) without using a memory compiler (see the picture).