The user user16145658 posted the following comment:
Processes suspend and resume in wait statements, here the implicit one
as a final statement with the sensitivity list defined for the
process. Signals update earlier in a simulation cycle than processes
execute. Updates are scheduled in a projected output waveform queue
which can have only one value for any time calculated from the current
simulation time plus the time in the waveform after clause (which
defaults 0). The last value written in the loop statement will be the
one scheduled. s and t could be variables instead. There's no
guarantee all those N operations can occur in one clock. –
For the little I know about this language, this seems helpful. I am going to offer help that may work in combination with this advice, since I am a Senior Developer with more than 15 years of professional software development experience.
First, get smaller parts of your code working. I get the impression that you typed all of this in, and you're just expecting all of it to work. I've been there myself... and had the same results.
So... break it up into smaller pieces, and test each piece. Then slowly integrate -- get two working pieces to work together, then another two, and so on. Code is best built like Tetris -- no gaps, out of simple pieces, ever building a solid foundation.
Also, another way... Get working the simplest thing that could possibly work. Then build on that, step by step.
As you improve your mental model, you may suddenly have an epiphany, and suddenly understand what's wrong with your previous code, and just reach in and fix it. True understanding is precious, and crucial for your forward progress.
Code is also like Sudoku -- it's impossible to fix errors because you don't know what's lying to you, you no longer have a firm foundation upon which to build well, and the cost of fixing it exponentially grows so much that the only real solution is to start over. This is reflected in the agile development methodology short development cycles which do better than waterfall methodology, improving the growing foundation by ensuring correctness as they continue to grow. The book Code Complete says that "Quality is free" and it pays you to do it right the first time, because every error is exponentially bad.
Another advice that I have is an interesting angle for this. Including an interactive microcontroller core, like a Forth core, in your FPGA allows you to put in some small primitives and then "probe" them interactively to see what the behavior is. There exists a family of Forth cores popular with EE's called the J1 family, which includes both VHDL and SystemVerilog cores. This amounts to including a resident monitor in the FPGA itself, which can be used to interactively probe your generated fabric from the inside, to see how it really behaves. And you can add your own growing set of FPGA analysis/development tools to the Forth cores, which will speed up the whole process.
If you're interested in pursuing this avenue, there is a non-J1-derivative SystemVerilog Forth core by a Facebook group called AI and Robotics, of which I am a member. The leader of the group, Don Golding, has regularly done presentations on progress at the Silicon Valley Forth Interest Group which I also regularly attend. We use this board, having the great Lattice UltraPlus ICE40UP5K FPGA with 5.3K LUTs, 1Mb SPRAM, 120Kb DPRAM, and 8 Multipliers. There have been some excellent presentations by Christopher Lozinski, a PhD student developing some Forth boards as part of his degree, especially his talk on the Review of Soft Core Forth Processors -- Christopher Lozinski -- 2023-08-26.
There is also a J1-derivative VHDL Forth core at OpenCores called the H2 Forth SoC, which looks pretty good. Just reading its VHDL code might be interesting, or give you some ideas.
You will find that the Forth cores are the smallest of FPGA cpu cores that exist, as that has been their mission from the beginning. Both small and simple (comparatively). This, and its famous interactive development ability, may be why they continue to be used on NASA missions and satellites.
And if you don't know Forth, the outstanding pico-ice RP2040 plus Lattice iCE40UP5K FPGA (for $35-USD as of Dec. 5, 2023) has the same FPGA our "AI and Robotics" group uses, but also a Raspberry Pi processor as well, which means that you can get a similarly interactive MicroPython REPL running on the RP2040 Pi chip and probe the FPGA from the outside, which is probably not nearly as good as being in the same fabric.
Full disclosure: I have nothing to profit from the sale of any of these boards. But we may need some people in our group who love to whip up FPGA boards, so feel free to join our "AI and Robotics" group.