I have noticed that when running gsch2pcb to convert a gEDA gschem schematic to a pcb layout that certain components that are properly connected in the schematic are unconnected in the PCB layout. In particular, transistors from the stock symbol library are affected but this has been seen for some other stock components too. (gschem version - Ubuntu x64)

To demonstrate this I created a new schematic as below a simple transistor circuit

Then checked the connections (using gnetlist -g drc2 demo.sch -o /dev/stdout) to ensure everything is connected up. All components have been assigned valid footprints.

pat@frog:/tmp/x$ gnetlist -g drc2 x.sch -o /dev/stdout
Loading schematic [/tmp/x/x.sch]
Checking non-numbered parts...

Checking duplicated references...

Checking nets with only one connection...

Checking pins without the 'pintype' attribute...

Checking type of pins connected to a net...

Checking unconnected pins...

Checking slots...

Checking duplicated slots...

Checking unused slots...

No warnings found. 
No errors found. 

This is then converted to a pcb layout using gsch2pcb and the netlist file loaded and we see the following ratsnest (I autoplaced the components as well): buggy pcb layout

So why is the NPN transistor being ignored? It is a standard gEDA symbol (npn-3.sym) and a standard footprint (TO92) from the PCB library. I both loaded the generated netlist file and executed the generated .cmd file and both these files list the pins on Q1. The netlist below has all 3 pins of Q1 connected to something.

pat@frog:/tmp/x$ cat x.net 
unnamed_net3    R3-2 LED1-2 
unnamed_net2    LED1-1 Q1-C R2-1 
+5V S1-2 R2-2 
GND R3-1 Q1-E R1-1 
unnamed_net1    Q1-B S1-1 R1-2 
  • \$\begingroup\$ gsch2pcb runs gnetlist on it's own and generates a netlist file. Do you have the same problem when using that? Also, are the netlist files from the two cases identical? \$\endgroup\$ Commented May 13, 2013 at 13:13
  • \$\begingroup\$ Yes - the gnetlist command I gave doesn't generate a netlist file (gnetlist -g drc3 x.sch -o /dev/stdout) will just run the drc2 check and output to stdout. The x.net file I gave at the end was actually generated from gsch2pcb. \$\endgroup\$
    – patthoyts
    Commented May 13, 2013 at 13:26
  • 1
    \$\begingroup\$ TO92 uses the 1, 2, 3 nomenclature while npn-3 used the C,E,B nomenclature for the pins. Rename the pins on the symbol and you should be fine, most likely. \$\endgroup\$ Commented May 13, 2013 at 13:33
  • \$\begingroup\$ You are right - it is the pin names. I realised there is a log window in PCB and in here I see "WARNING! Pin number ending with 'C' encountered in netlist file" for each of these pins (E, C and B). It seems the generic NPN symbols is buggy and we should be using the more specific symbols (2N2222 or BC547 both work correctly when I tried.) If you make an answer - I can accept it. \$\endgroup\$
    – patthoyts
    Commented May 13, 2013 at 14:29

2 Answers 2


The generic NPN symbols use B-C-E as the pin names and not 1-2-3 as the TO92 footprint does, which is a generic package and not used only for transistors.

The nets are connected to Q1's B, C, E pads which don't actually exist, so you have no corresponding lines on your ratsnest.

You should edit the symbols to use the 1-2-3 names for the pins (in pinnumber). These should match the names of the pads in the footprints.

It's something of a philosophical argument on how it should be done conventionally. For the moment, using 1-2-3 seems cleaner to me, personally, but it helps to remember that transistors aren't always in TO92, and therefore B-C-E may be easier to switch from one package to another (though you would then have an alternative footprint to TO92 in your library specifically for transistors)

  • 3
    \$\begingroup\$ This conflict between schematic pin names and PCB pin numbers is common to many CAD systems. I prefer to leave the shcematic pins as E-B-C, and make multiple PCB footprints with the pins renumbered as required, such as: TO92-EBC, TO92-ECB, TO-92-DGS... \$\endgroup\$ Commented May 13, 2013 at 17:32

Instead of editing the symbol, you can accomplish the same effect using slots feature. Add the following attributes to the transistor: slot=1 numslots=1 slotdef=1:3,2,1

Numbers in slotdef after 1: represent package pin numbers, in pinseq order. In the example above, for npn-3 symbol, C has pinseq=1 and will be assigned pin 3, B has pinseq=2 and will be assigned pin 2, and E has pinseq=3 and will be assigned pin 1.

Other transistors may have different pin assignments. For example, use slotdef=1:2,1,3 for an MJE305 in TO220W package. If you keep editing the symbol you will keep breaking your previous designs. You can also create a bunch of clones with different pin assignments, but that can get out of hand pretty quickly if you use many different types of transistors.

  • \$\begingroup\$ Thanks from a gEDA beginner! Actually the most practical way to avoid crippling the disk with useless footprint files! Now the trick is to make all transistors inherit from the first two attributes. I guess I can figure it out on my own. \$\endgroup\$
    – user59864
    Commented Mar 12, 2015 at 11:27

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