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I'm currently designing an CMOS comparator and I'm a little bit lost regarding sizing the transistors. I was taught to use the Id formula, but for that to work I need to have muCox, and I do not. Can't calculate muCox either because I don't have W/L ratio, since it's what I'm trying to calculate.

Is there any other way to get the W/L ratio for each NMOS/PMOS knowing Id, Vgs and Vds?

For now I want all transistors in saturation, I'll change that once I find a solid method to size everything. Below is the topology I'm trying to size.

Comparator topology I'm trying to size

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If you know Id, Vgs, and Vds, and a Virtuoso device model, you have enough information to solve for an approximate shape ratio under a few assumptions (namely, no body effect, if applicable you've decided between nominal/low-Vt/native/RF transistors and chosen a specific one, etc)

Even though you don't have a muCox, your spice/spectre models will include a vast number of process-specific parameters that will provide the same unknown as muCox does, just with a much higher degree of precision.

You can pick a length based on your speed and approximate R_out requirement(1), bias a transistor with a constant Vgs and Vds, and sweep the width ratio until the correct drain current is achieved. This will get you a solution at one corner (probably the nominal one), and you may need to iterate on both length and width if you aren't hitting all specs, and will set your inversion coefficient (2) for you.

You'll also want to note that the performance will vary outside the typical corner - presumably your Vgs, Vds, and headroom will change a bit as long as you're feeding a constant current

Notes:

(1) - Higher length makes for a slower transistor, but with better output impedance and intrinsic gain.

(2) - At low inversion coefficient (weak inversion) transconductance efficiency (gm/Id) is high, but speed is low. At high inversion coefficient gm/Id is low, but speed is higher. I give plots in this answer I wrote a few years back. As further reading, if you want a methodology that relates gm/id to high-speed small-signal performance, you may want to consider gm/Id based design, I have written up a past answer here. I don't know enough about your current topology and criteria to know whether it is applicable (and this question is not a duplicate).

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  • \$\begingroup\$ Appreciate your answer! I've added the topology I'm following. I'm not aiming for a fast comparator since it'll be used within a 10 bits IADC for temperature values, but I'm not sure if a too slow circuit would be acceptable. As for the model parameters you talked about, are those the ones shown in Print > Model parameters? \$\endgroup\$
    – Scully
    Dec 1, 2023 at 0:41
  • \$\begingroup\$ @Scully Regarding model parameters - not quite, they're simply the model parameters that your fab/foundry provides when they send you a process development kit (PDK). If you can run a simulation with MOSFETs from your process, all those parameters should be ready, and you should be ready to sweep. \$\endgroup\$
    – nanofarad
    Dec 1, 2023 at 1:23

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