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I have the schematic for a wind turbine charge controller from here.

Larger circuit diagram showing context of original post.

What is the purpose of the two interconnected NOR gates in the middle of the schematic?

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  • \$\begingroup\$ Please reference the source for the image, inline with stack guidance. \$\endgroup\$
    – colintd
    Dec 1, 2023 at 15:52

3 Answers 3

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S-R Latch

The two NOR gates form an S-R ("Set"-"Reset") latch.

enter image description here

(Symbol from linked source.)

The two outputs 3 (Q) & 4 (not Q) are intended to be complements of each other.

Whilst input 1 (RESET) & 6 (SET) are both low, the state of Q & not-Q will not change (i.e. they are "latched"). This is due to the feedback from each output to the input of the other gate.

  • If 6 (SET) goes high, 3 (Q) goes high, and 4 (not Q) goes low.

  • If 1 (RESET) goes high, 3 (Q) goes low, and 4 (not Q) goes high.

  • If 1 & 6 are both high (SET and RESET at the same time), the Q / not-Q complementary state breaks down, with both outputs being low.

(The "S-R latch" is also known as an "S-R flip-flop".)

Operational significance

In the full schematic, we can see an op-amp/comparator implementing an upper "dump" threshold on the turbine output (which the "dump" button can force) and another op-amp/comparator implementing a lower "charge" threshold (which the charge button can force).

One would expect the two thresholds to be set so there is a dead zone in the middle, and as such only one will be active at once (meeting the input requirements for the S-R latch).

The latch means the current state is held until the opposite threshold is hit. This provides latching of the "Dump"/"Charge" relay state, only switching from one state to the other either when the buttons are manually pressed, or when the turbine voltages hits the opposite threshold.

You would normally expect the two thresholds to be significantly different, to provide hysteresis and prevent "chatter" of the relay.

The two complementary outputs are also used to drive the "Charge" & "Dump" leds.

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  • \$\begingroup\$ but since there is a current through both in this circuit would that not mean they both have an input of 1 from the start? how does the input change? \$\endgroup\$
    – user357057
    Dec 1, 2023 at 16:16
  • \$\begingroup\$ Have a look at the tutorial at build-electronic-circuits.com/s-r-latch (or other similar tutorials) which take you through the operation of the latch. \$\endgroup\$
    – colintd
    Dec 1, 2023 at 16:39
  • \$\begingroup\$ In terms of the full circuit, you have an upper "dump" threshold (which the "dump" button can force) and a lower "charge" threshold (which the charge button can force), with the two thresholds set so there is a dead zone in the middle, so only one will be active at once. The latch means a clean flip from one state to the other , when the opposite threshold is hit, but in between a stable state. \$\endgroup\$
    – colintd
    Dec 1, 2023 at 16:43
  • \$\begingroup\$ The two 3K3 resistors are just pull-up resistors, with the actual input states to the latch being defined by the state of the comparators. \$\endgroup\$
    – colintd
    Dec 1, 2023 at 16:48
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    \$\begingroup\$ @user357057 4001 is a CMOS gate and no current flows through the gate. (Current can flow out of the output of the gate if needed). On startup, if the voltage is in the middle of the two settings so both comparators are off, then each NOR gate is trying to turn the other one off, due to random variation one of them has slightly more voltage or whatever and it starts up in a random state. \$\endgroup\$
    – user253751
    Dec 2, 2023 at 0:55
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That is a basic SR flip-flop circuit with active high set and reset inputs.

The two inputs can set the state of the output with a high pulse, and it will remember the state until there is a pulse to set it to the other state.

It is basically one bit of memory with two inputs to write a 0 or 1 to the memory and the outputs provide the state of the current value in memory.

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  • \$\begingroup\$ would you mind explaining what that is? or does \$\endgroup\$
    – user357057
    Dec 1, 2023 at 15:59
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    \$\begingroup\$ @user357057 Google can be your friend here, see geeksforgeeks.org/sr-flip-flop \$\endgroup\$
    – John D
    Dec 1, 2023 at 16:07
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This pair of gates is a R-S flip-flop.

In this circuit this allows start and stop levels to easily be set independently

The designer for some reason chose not use analogue feedback to give this feature, as this looks like a one off the cost of the extra part is probably cheaper than the extra effort to make a reliable analogue posiitive feedback path.

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