I have the below code in vitis hls, the STREAM is powered by the AXI interface ports that are supplied to the function.
func1(){
static hls::stream<int> buffer("buffer1");
#pragma HLS STREAM variable=buffer depth=100
#pragma HLS DATAFLOW
//Algorithm
}
func2(){
static hls::stream<int> buffer2("buffer2");
#pragma HLS STREAM variable=buffer2 depth=100
#pragma HLS DATAFLOW
//Algorithm
}
acc(int type){
//AXI interface
if(type){
func1();
}else{
func2();
}
}
Also, I have a testbench to call the acc function with both types. The problem I have is that if I run only one of the functions then the C/RTL COSIMULATION works correctly, but if I want to do with both, my test fails and the final RTL.
Do you have any idea what is happens, and how can I solve it?