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I'm designing a single stage MOSFET amp for use with a 10k ohm load (R3) and I'm getting abysmal gain. How should I change the values of my biasing resistors?

enter image description here enter image description here

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  • \$\begingroup\$ I'm more familiar with silicon carbide than silicon, but 10 μm feels like a very long channel, and 20:1 a pretty poor W:L ratio. Are you sure your FET dimensions are reasonable? \$\endgroup\$
    – Hearth
    Dec 2, 2023 at 3:39
  • \$\begingroup\$ For reference, some of the smaller silicon carbide devices I've worked with have a channel length of about 1 μm (if I recall correctly--I'm just the test engineer, not the designer), and width of 30 cm (which I'm certain of). I'm sure standard silicon FETs don't have W/L ratios quite that extreme, but 20 feels very low. \$\endgroup\$
    – Hearth
    Dec 2, 2023 at 3:41
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    \$\begingroup\$ The gain is close to nominal. Why do you call it abysmal? \$\endgroup\$
    – tobalt
    Dec 2, 2023 at 7:53
  • \$\begingroup\$ Looks pretty OK to me. \$\endgroup\$
    – Andy aka
    Dec 2, 2023 at 9:55
  • \$\begingroup\$ @Hearth Ballpark classic era IC values are a couple µm, contemporary to SPICE's introduction and hence the 2µm defaults. Give or take physical and modeling parameters, 1-10µm length might be a typical baseline, with W/L ~ 20 say for a logic gate output transistor, i.e. good for low 10s mA. Which is probably about right for the resistors shown here, but that depends on those parameters, and actual threshold voltage and so on; showing DC voltages would be welcome here. \$\endgroup\$ Dec 2, 2023 at 16:44

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The nice sinusoidal output suggests that biasing is OK (at least for these small signals), and I don't see a problem. With that configuration you can expect a voltage gain \$A\$ of roughly:

$$ A \approx \frac{R_D}{R_S} = \frac{2k\Omega}{280\Omega} = 7 $$

From that graph, the output seems to peak at about 30mV. Given an input of 5mV peak, gain is:

$$ A \approx \frac{30mV}{5mV} = 6 $$

The discrepancy between theroetical and measured gain can no doubt be attributed to:

  • slight attenuation by the two high-pass filters, formed by (C1, R1 and R2) and (C2 and R3), and

  • loading of the non-zero output impedance by R3, 10kΩ

To see performance closer to the theoretical \$A=7\$:

  • Increase input signal frequency. Try 10kHz

  • Increase R3. Try 100kΩ

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i'm curious, what is the dc bias current and the voltage of the source?

audioguru and simon already explain the expected gain.

but one point of your image calls that approximation into question... your W/L is strange...

small signal analysis. Your signal is 1 decade above the corner frequency of the highpass RC filter at the output so

Av = Gm.Rout. Rout = Rd || R3 || [ro1(gm1.Rs+1)]. Rout ~ Rd || R3 Gm = gm1/(1+gm1.Rs). Av ~ (Rd || R3)/ Rs

With a "normal" W/L (think 5, 10) and sufficient DC biasing (Audioguru's suggestion) we make the gm1.Rs >> 1 approximation and Av ~ (Rd||R3)/Rs = 5.96 (audioguru)

but as the comments point out... the difference in gain is not as "abysmal" as you might think it is.

Few ways to increase your gain a) remove source degeneration. Remove Rs and you remove the negative feedback. negative feedback is decreasing your open-loop gain, which would be gm.Rd

gm is transconductance. either look it up in a datasheet or compute it from transistor sweeps

you may decide to keep negative feedback but decrease Rs

b) increase your VGS bias. so make R2 bigger to adjust the voltage divider UP and/or decrease (or remove) the voltage drop across the source resistance

c) gm1 = mu.Cox.(W/L)(VGS-Vth)^2. Increase W/L ratio. Raise Vgs. You have a lot of room for the gate bias...

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Your Mosfet has no part number then it might have a gate to source threshold voltage of 4V like in your circuit. Then it conducts only 0.25mA.
the 10k load is parallel to the 2k drain resistor creating a total of 1.67k ohms.
The gain is 1.67k/280 (the source resistor is 280 ohms)= 5.96 times.

Your circuit measures a gain of 24.96/4.55= 5.49 times which is a little low because the gate-source voltage is a little low.
The gain will be higher if you increase the gate-source DC voltage and increase the RD/RS ratio.

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Example below with 2N7000 based mosfet amplifier.

By Partially by-passing the source resistance I have more than doubled the gain.

Mosfet Amplifier

If the input signal is kept to a small amplitude (to avoid saturation) you can further increase the gain by increasing the drain resistance which reduces the quiescent drain bias. Here we have a gain of over 18.

Mosfet Amplifier

We can increase the gain by a very large amount by fully bypassing the source resistance, reducing the gate bias and increasing the drain resistance. In this situation the bias at the drain is quite low so, again, the input signal amplitude must be kept quite low to avoid saturating the amplifier. In this case we are reducing the gate bias which reduces the source bias, reducing the source current. Because the source (and drain) current has reduced we can increase the drain resistance which drops the drain bias but also increases the gain. Gain in this circuit example is about 108.

Mosfet Amplifier

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