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I have 2n3906 transistor. I want 24vdc output when 0vdc and 0vdc output when 10vdc. I want to give this output to plc which has 2.5mA min current requirement for logic high. I have 24vdc rail available

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  • \$\begingroup\$ You won't adequately achieve this with a single PNP transistor. So now, because you have a limited kit of parts you have to start explaining where you can cut into your requirements (and I mean significantly). If in fact you want a linear relationship between input and output, a more savage specification cut will be required. Of course, if you have op-amps and other more relevant silicon then it's less of a problem to get close to the specification. \$\endgroup\$
    – Andy aka
    Dec 2, 2023 at 17:42
  • \$\begingroup\$ To do this with pnp you are not able to achieve a common ground of both sources. If 12 and 24 sources are isolated each other it can be done since you can connect a plus rails together. \$\endgroup\$ Dec 2, 2023 at 17:46
  • \$\begingroup\$ Do you want to convert a digital signal or an analog value? \$\endgroup\$
    – Jens
    Dec 2, 2023 at 17:53
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    \$\begingroup\$ I assume you want to convert a digital voltage 0 to 10V to a digital voltage 0 to 24V, where the 0V is common to both input & output. Questions: Q1: Time delay: what is the maximum acceptable value for the time delay (from input changing by 50% to output changing by 50%) ? Q2: Output rise & fall times: what is the maximum acceptable values rise & fall times at the output? Q3: Input rise & fall times: what are the slowest times for rise & fall of the input signal that will occur? \$\endgroup\$ Dec 2, 2023 at 22:36
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    \$\begingroup\$ Cont'd: Q4: Input logic "0" threshold values: what is the expected voltage range for the input voltage amplitude that represents a logical "0"? Q5: Input logic "1" threshold values: what is the expected voltage range for the input voltage amplitude that represents a logical "1"? \$\endgroup\$ Dec 2, 2023 at 22:37

5 Answers 5

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The solution is a circuit similar to the one posted by Jens, but delete one resistor and add one 18 V zener diode. This prevents the transistor from conducting when the input is high.

enter image description here

When the input is low, 23.4 V is distributed across R1 and D1. D1 conducts, leaving approx. 5.4 V across R1. The device that is driving the input needs to be able to sink 1.2 mA or more in the low state. In this condition, Q1 is saturated and the output is at approx 23.8 V. R1 also limits the Q1 base current to a safe value.

For best long-term reliability, the max output current should be limited to 50% of the 2N3906 collector current rating. To increase the available output current while still holding Q1 in saturation, R1 can be decreased.

When the input is at 10 V, there is only 13.4 V across the input components. This is not enough to cause D1 to conduct, so it is basically an open circuit. R2 assures that Q1 is off, and R3 pulls the output to GND.

The input voltage transition level between Q1 being on and off is approx. 5.4 V, close to 50% of the specified input voltage range.

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Since you've added that you can use NPN transistors, this is a reliable way to do what you request. If you can invert the input by some other means you can eliminate Q1 and R1 (connect R4 to Q2 base).

schematic

simulate this circuit – Schematic created using CircuitLab

enter image description here

This should work also (and only uses PNP transistors!), but I would not recommend it (it won't simulate correctly, for one thing):

schematic

simulate this circuit

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  • \$\begingroup\$ Bonus points for an explanation of your second circuit.... are those backwards PNPs field expedient 5 or 6V zener (I.e. you're using their reverse breakdown)? \$\endgroup\$ Dec 4, 2023 at 9:28
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    \$\begingroup\$ Yes, using reverse E-B breakdown of (typically) about 9V each as as an 18V zener diode, so very similar to Analogkid as it turns out. \$\endgroup\$ Dec 4, 2023 at 11:20
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With these resistor values the output voltage changes at an input voltage of around 8 V.

If SW1 is open or V1 is at 0 V the base current of Q1 is high enough to provide close to 24 V at the PLC input (V_OUT).

Above 8 V at V_IN the voltage across R1 (= Vbe) is too low for a base current and Q1 turns off.

schematic

simulate this circuit – Schematic created using CircuitLab

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  • \$\begingroup\$ this is not working. output is constant 24v no matter if base signal is 0 or 10 \$\endgroup\$ Dec 2, 2023 at 21:16
  • \$\begingroup\$ "this is not working" are you referring to the linked simulation (which works), or a physical circuit you've wired up? \$\endgroup\$
    – Attie
    Dec 3, 2023 at 0:52
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4v7 zener as comparator, 2n3904 as inverter and 2n2222 buffer.

enter image description here

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For level-shifters where the voltages involved are well above 5V (ie: above normal IC logic levels), I prefer to use discrete designs based on a differential pair input stage followed by a logic output stage. This structure provides plenty of scope to tailor the circuit behaviour to suit the specific application, in regards to:

  • threshold voltage
  • degree of hysteresis
  • speed
  • available parts (eg: transistors, diodes, resistors, capacitors)

Image below: Over-all Schematic (Inverting)
The circuit is presented below, and is comprised of four (4) main sections. This circuit is inverting but can be easily adapted to be non-inverting if required. A detailed description can be found later in this answer.
enter image description here

Performance:
The circuit as presented here has the following behaviour:
Vin neg threshold ~ 3.8V (=1.2V below 5.0V)
Vin pos threshold ~ 6.3V (=1.3V above 5.0V)
Vin threshold hysteresis ~ 2.5V
Vout rise time ~0.5us
Vout fall time ~2us
Useful for square-wave inputs with frequency up to 10kHz.

The waveforms below show circuit performance with both slow and fast input signals.

Image below: Waveform set 1, Vin thresholds
Vin is a pulse with rather slow edges (1ms rise and fall times), which shows the Vin high and low thresholds.
enter image description here

Image below: Waveform set 2, Speed
Vin is a 10kHz square-wave, with fast edges (1us rise & fall times) with pulse width=20us, which shows the delay time and output rise & fall times.
enter image description here

Detailed Description and Design Notes

Section 1: Diff Pair.
R1 (in conjunction with Vref) sets the bias current, in this case about 500uA. This current will drive the output stage, so select this current to ensure Q3 has plenty of base current to drive the intended load. In this case, I used a ratio of 10, ie: 5mA of output current, so 0.5mA of current in R1. Other ratio values can be used, but this is a starting point, and the design will tolerate a wide range without too much trouble.

One can think of this stage as behaving as a switched current source (sink): the input voltage simply selects where the current in R1 flows: it flows either in the collector of Q1, or the collector of Q2. Hence, the resistors selected to be in the collector circuits, R2 & R3, are not that critical; in the limiting case, R2 may be removed altogether, and R3 can be replaced with a short.

D3 & D4 protect the base-emitter junctions of Q1 and Q2 from excessive reverse voltage; these may be excluded depending the devices used for Q1 & Q2, and the behaviour of the circuit under all worst-case conditions (I prefer to leave them in regardless as cheap insurance & peace of mind).

Section 2: V Ref.
This creates the voltage at which the comparator will switch when no hysteresis is applied. In this case, it is a very simple resitive divider network, but you can make this as simple or as sophisticated as required. I choose to use resistors rather than zener diodes, simply because I don't want to carry a bunch of different zener diodes in stock - whereas I already have all the resistor values. R11 is used to tweak the threshold, in this case it can be left out.

Some design rules to consider are: (a) how much bias current it draws, and (b) its internal impedance should be one-tenth that of R7 & R9 (so that R7 & R9 dominate the hysteresis, rather than the Vref network). R7 and R9 should dominate the internal impedances of their respective signals so that the circuit can be easily converted to inverting operation with minimal changes to either behaviour, or component values.

Section 3: Output.
This is a very simple single-transistor inverter with a Bakers clamp. Select R14 such that it draws between 5 & 10% of the base current drive available from R1 via Q2. Value of R8 is not critical, here is it set to same as R3. Note that the upper current limit for the current into Q1 collector is set by R1, not by the components in Q1 collector.

Diodes D1 & D2 form the Bakers clamp, which prevents Q3 from going into deep saturation thus greatly speeding up the turn-off of Q3 (speeds up the high-to-low transition at Vout, ie: Vout negative edge). These diodes may be omitted for applications where high speed is not required, however, in that case the values of resistors R14 & R8, as well as R2 and R3, may need to be reviewed.

Section 4: Feedback.
R10 in conjunction with R7 sets up the hysteresis of the comparator function so that the overall behaviour is that of a Schmitt trigger, refer link:
https://en.wikipedia.org/wiki/Schmitt_trigger

C1 and R16 control the rate-of-change of the output voltage during the switching transitions. The RC time-constant should be sufficient to suit the speed of the transistors used (Q1, Q2, & Q3) but sufficiently short to ensure good operation at the maximum expected frequency of the input signal. Also, they can be adjusted to get symmetrical rise and fall times (not done here).

Change from Inverting to Non-Inverting
Output can be changed to non-inverting by either:

  • connecting the output stage and feedback to Q1, rather than Q2 as shown here (& be sure to swap over the resistors in the collectors of Q1 & Q2), or
  • swapping over the roles of nodes Vsig1 and Vref1.
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